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hdmirx: update the latest setting of phy. [1/1]

Browse Source 
PD#SWPL-2803

Problem:
PHY configuration update

Solution:
1.update phy setting for low_frequency;
2.rm the useless FSM code;
3.optimize the phy configeration interfaces;
4.fix PS4 Pro flashing black&blue screen issue;

Verify:
txlx tl1

Change-Id: I0bea4fa6ec5d9284ed04845b06c3583128f3332d
Signed-off-by: Lei Yang <lei.yang@amlogic.com>
This commit is contained in:
Lei Yang
2018-12-10 18:34:06 +08:00
committed by Jianxin Pan
parent 8617565bd5
commit 88f482c169
8 changed files with 400 additions and 814 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.c
View File

@@ -361,7 +361,7 @@ void hdmirx_dec_close(struct tvin_frontend_s *fe)
* reset the vdac) to avoid noise issue
*/
/* For txl,also need to keep bandgap always on:SWPL-1224 */
/* if (rx.hdmirxdev->data->chip_id == CHIP_ID_TXL) */
/* if (rx.chip_id == CHIP_ID_TXL) */
/* vdac_enable(0, 0x10); */
/* open_flage = 0; */
rx.open_fg = 0;
@@ -602,7 +602,7 @@ void hdmirx_set_timing_info(struct tvin_sig_property_s *prop)
/* 420 : hdmiout clk = pixel clk * 2 */
/* 422 : hdmiout clk = pixel clk * colordepth / 8 */
/* 444 : hdmiout clk = pixel clk */
if (rx.hdmirxdev->data->chip_id < CHIP_ID_TL1) {
if (rx.chip_id < CHIP_ID_TL1) {
/* tl1 need verify this bug */
if ((rx.pre.colordepth > E_COLORDEPTH_8) &&
(prop->fps > 49) &&
@@ -1717,7 +1717,7 @@ static void rx_phy_resume(void)
void rx_emp_resource_allocate(struct device *dev)
{
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
if (rx.chip_id == CHIP_ID_TL1) {
/* allocate buffer */
if (!rx.empbuff.storeA)
rx.empbuff.storeA =
@@ -1762,7 +1762,7 @@ void rx_tmds_resource_allocate(struct device *dev)
/*phys_addr_t p_addr;*/
/*struct page *pg_addr;*/
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.empbuff.dump_mode == DUMP_MODE_EMP) {
if (rx.empbuff.pg_addr) {
dma_release_from_contiguous(dev,
@@ -2002,7 +2002,7 @@ static int hdmirx_probe(struct platform_device *pdev)
if (hdevp->data) {
rx.chip_id = hdevp->data->chip_id;
rx_pr("chip id:%d\n", rx.hdmirxdev->data->chip_id);
rx_pr("chip id:%d\n", rx.chip_id);
rx_pr("phy ver:%d\n", rx.hdmirxdev->data->phy_ver);
} else {
/*txlx chip for default*/
@@ -2207,8 +2207,8 @@ static int hdmirx_probe(struct platform_device *pdev)
clk_rate = clk_get_rate(hdevp->skp_clk);
}
}
if ((rx.hdmirxdev->data->chip_id == CHIP_ID_TXLX) ||
(rx.hdmirxdev->data->chip_id == CHIP_ID_TXHD)) {
if ((rx.chip_id == CHIP_ID_TXLX) ||
(rx.chip_id == CHIP_ID_TXHD)) {
tmds_clk_fs = clk_get(&pdev->dev, "hdmirx_aud_pll2fs");
if (IS_ERR(tmds_clk_fs))
rx_pr("get tmds_clk_fs err\n");
@@ -2233,7 +2233,7 @@ static int hdmirx_probe(struct platform_device *pdev)
clk_rate/1000000);
}
#endif
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
if (rx.chip_id == CHIP_ID_TL1) {
/*for audio clk measure*/
hdevp->meter_clk = clk_get(&pdev->dev, "cts_hdmirx_meter_clk");
if (IS_ERR(hdevp->meter_clk))
@@ -2317,6 +2317,7 @@ static int hdmirx_probe(struct platform_device *pdev)
rx_pr("warning: no rev cmd mem\n");
rx_emp_resource_allocate(&(pdev->dev));
hdmirx_hw_probe();
hdmirx_init_params();
hdmirx_switch_pinmux(&(pdev->dev));
#ifdef CONFIG_AMLOGIC_LEGACY_EARLY_SUSPEND
register_early_suspend(&hdmirx_early_suspend_handler);

8
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h
View File

@@ -46,7 +46,7 @@
*
*
*/
#define RX_VER2 "ver.2018/11/22"
#define RX_VER2 "ver.2018/12/18"
/*print type*/
#define LOG_EN 0x01
@@ -57,6 +57,7 @@
#define EQ_LOG 0x20
#define REG_LOG 0x40
#define ERR_LOG 0x80
#define EDID_LOG 0x100
#define VSI_LOG 0x800
/* 50ms timer for hdmirx main loop (HDMI_STATE_CHECK_FREQ is 20) */
@@ -363,7 +364,10 @@ struct phy_sts {
uint32_t pll_rate;
uint32_t clk_rate;
uint32_t phy_bw;
uint32_t cablesel;
ulong timestap;
uint32_t err_sum;
uint32_t eq_data[256];
};
struct emp_buff {
@@ -432,7 +436,7 @@ struct rx_s {
unsigned int pwr_sts;
/* for debug */
/*struct pd_infoframe_s dbg_info;*/
struct phy_sts physts;
struct phy_sts phy;
struct emp_buff empbuff;
};

6
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_edid.c
View File

@@ -1121,7 +1121,8 @@ unsigned char get_atmos_offset(unsigned char *p_edid)
do {
tag_data = p_edid[tag_offset];
if ((tag_data & 0xE0) == 0x20) {
rx_pr("audio_\n");
if (log_level & EDID_LOG)
rx_pr("audio_");
aud_length = tag_data & 0x1F;
break;
}
@@ -1148,7 +1149,8 @@ unsigned char rx_edid_update_atmos(unsigned char *p_edid)
p_edid[offset] = 1;
else
p_edid[offset] = 0;
rx_pr("offset = %d\n", offset);
if (log_level & EDID_LOG)
rx_pr("offset = %d\n", offset);
}
return 0;
}

6
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_eq.c
View File

@@ -181,9 +181,8 @@ void eq_dwork_handler(struct work_struct *work)
cancel_delayed_work(&eq_dwork);
/* for tl1 no SW eq */
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
if (rx.chip_id == CHIP_ID_TL1)
return;
}
for (i = 0; i < NTRYS; i++) {
if (SettingFinder() == 1) {
@@ -489,7 +488,8 @@ int rx_eq_algorithm(void)
uint8_t pll_rate = hdmirx_rd_phy(PHY_MAINFSM_STATUS1) >> 9 & 3;
/* for tl1 no SW eq */
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
if (rx.chip_id == CHIP_ID_TL1) {
hdmirx_phy_init();
eq_sts = E_EQ_FINISH;
return 1;
}

517
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c
View File

@@ -64,14 +64,6 @@ static bool phy_fast_switching;
static bool phy_fsm_enhancement = true;
/*unsigned int last_clk_rate;*/
/* SNPS suggest to use the previous setting 0x3f when handle eq issues to
* make clk_stable bit more stable(=1),but 0x3f may misjudge 46.25~92.5
* TMDSCLK as 25~46.25M TMDSCLK,pll_rate&REQUESTCLK will become
* not correct. so revert the setting to the default value 0x6
* according to the PHY spec
*/
static uint8_t phy_lock_thres = 0x6;
static uint32_t phy_cfg_clk = 24000;
static uint32_t modet_clk = 24000;
/* top_irq_en bit[16:13] hdcp_sts */
@@ -87,7 +79,6 @@ int pdec_ists_en;/* = AVI_CKS_CHG | DVIDET | DRM_CKS_CHG | DRM_RCV_EN;*/
uint32_t packet_fifo_cfg;
int pd_fifo_start_cnt = 0x80;
/* Controls equalizer reference voltage. */
int eq_ref_voltage = 0x1ea;
int hdcp22_on;
MODULE_PARM_DESC(hdcp22_on, "\n hdcp22_on\n");
module_param(hdcp22_on, int, 0664);
@@ -98,16 +89,16 @@ module_param(hdcp22_on, int, 0664);
* SECURE_MODE:secure OS path
*/
int hdcp14_key_mode = NORMAL_MODE;
int aud_ch_map;
int ignore_sscp_charerr = 1;
int ignore_sscp_tmds = 1;
int find_best_eq;
int eq_try_cnt = 50;
/*------------------------variable define end------------------------------*/
static int check_regmap_flag(unsigned int addr)
{
return 1;
}
/*
@@ -122,7 +113,7 @@ unsigned int hdmirx_rd_dwc(unsigned int addr)
int data;
unsigned long dev_offset = 0x10;
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
if (rx.chip_id == CHIP_ID_TL1) {
data = rd_reg(MAP_ADDR_MODULE_TOP,
addr + reg_maps[MAP_ADDR_MODULE_TOP].phy_addr);
} else {
@@ -158,7 +149,7 @@ void hdmirx_wr_dwc(unsigned int addr, unsigned int data)
ulong flags;
unsigned int dev_offset = 0x10;
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
if (rx.chip_id == CHIP_ID_TL1) {
wr_reg(MAP_ADDR_MODULE_TOP,
addr + reg_maps[MAP_ADDR_MODULE_TOP].phy_addr, data);
} else {
@@ -290,7 +281,7 @@ unsigned int hdmirx_rd_top(unsigned int addr)
unsigned int dev_offset = 0;
unsigned int tempaddr = 0;
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
if (rx.chip_id == CHIP_ID_TL1) {
dev_offset = TOP_DWC_BASE_OFFSET +
reg_maps[MAP_ADDR_MODULE_TOP].phy_addr;
if ((addr >= TOP_EDID_OFFSET) &&
@@ -337,7 +328,7 @@ void hdmirx_wr_top(unsigned int addr, unsigned int data)
unsigned long dev_offset = 0;
unsigned int tempaddr = 0;
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
if (rx.chip_id == CHIP_ID_TL1) {
dev_offset = TOP_DWC_BASE_OFFSET +
reg_maps[MAP_ADDR_MODULE_TOP].phy_addr;
if ((addr >= TOP_EDID_OFFSET) &&
@@ -701,11 +692,7 @@ void hdmirx_phy_pddq(unsigned int enable)
void hdmirx_wr_ctl_port(unsigned int offset, unsigned int data)
{
unsigned long flags;
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
/* need to do for tl1 ... */
} else {
if (rx.chip_id < CHIP_ID_TL1) {
spin_lock_irqsave(&reg_rw_lock, flags);
wr_reg(MAP_ADDR_MODULE_TOP, hdmirx_ctrl_port+offset, data);
spin_unlock_irqrestore(&reg_rw_lock, flags);
@@ -721,7 +708,7 @@ void hdmirx_top_sw_reset(void)
unsigned long dev_offset = 0;
spin_lock_irqsave(&reg_rw_lock, flags);
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
if (rx.chip_id == CHIP_ID_TL1) {
hdmirx_wr_top(TOP_SW_RESET, 1);
udelay(1);
hdmirx_wr_top(TOP_SW_RESET, 0);
@@ -1027,7 +1014,7 @@ bool is_clk_stable(void)
{
int clk = false;
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
if (rx.chip_id == CHIP_ID_TL1) {
/* sqofclk */
clk = hdmirx_rd_top(TOP_MISC_STAT0) & 0x1;
} else {
@@ -1223,7 +1210,7 @@ static int TOP_init(void)
hdmirx_wr_top(TOP_VID_CNTL2, data32);
}
data32 = 0;
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
if (rx.chip_id == CHIP_ID_TL1) {
/* n_cts_auto_mode: */
/* 0-every ACR packet */
/* 1-on N or CTS value change */
@@ -1231,12 +1218,12 @@ static int TOP_init(void)
}
/* delay cycles before n/cts update pulse */
data32 |= 7 << 0;
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1)
if (rx.chip_id == CHIP_ID_TL1)
hdmirx_wr_top(TOP_TL1_ACR_CNTL2, data32);
else
hdmirx_wr_top(TOP_ACR_CNTL2, data32);
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
if (rx.chip_id == CHIP_ID_TL1) {
data32 = hdmirx_rd_dwc(DWC_HDCP_CTRL);
/* 0: Original behaviour */
/* 1: Balance path delay between non-HDCP and HDCP */
@@ -1460,7 +1447,7 @@ void rx_hdcp14_config(const struct hdmi_rx_hdcp *hdcp)
#if 0
void rx_set_term_enable(bool enable)
{
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
if (rx.chip_id == CHIP_ID_TL1) {
/* need to do : for tl1 */
} else
hdmirx_wr_bits_phy(PHY_MAIN_FSM_OVERRIDE1,
@@ -1472,7 +1459,7 @@ void rx_set_term_value(unsigned char port, bool value)
{
unsigned int data32;
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
if (rx.chip_id == CHIP_ID_TL1) {
/* need to do : for tl1 */
data32 = rd_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0);
if (port < E_PORT3) {
@@ -1570,7 +1557,7 @@ void rx_force_rxsense_cfg(uint8_t level)
unsigned int term_ovr_value;
unsigned int data32;
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
if (rx.chip_id == CHIP_ID_TL1) {
/* enable terminal connect */
data32 = rd_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0);
if (level) {
@@ -1666,7 +1653,7 @@ void hdcp22_clk_en(bool en)
((0 << 25) |
(1 << 24) | /* [ 24] Enable gated clock */
(0 << 16)));
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1)
if (rx.chip_id == CHIP_ID_TL1)
/* TL1:esm related clk bit9-11 */
hdmirx_wr_bits_top(TOP_CLK_CNTL, MSK(3, 9), 0x7);
else
@@ -1843,7 +1830,7 @@ void clk_init(void)
data32 |= 0 << 31; /* [31] disable clkgating */
data32 |= 1 << 17; /* [17] audfifo_rd_en */
data32 |= 1 << 16; /* [16] pktfifo_rd_en */
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
if (rx.chip_id == CHIP_ID_TL1) {
data32 |= 0 << 8; /* [8] tmds_ch2_clk_inv */
data32 |= 0 << 7; /* [7] tmds_ch1_clk_inv */
data32 |= 0 << 6; /* [6] tmds_ch0_clk_inv */
@@ -1949,7 +1936,7 @@ int hdmirx_audio_init(void)
data32 |= acr_mode << 0;
hdmirx_wr_top(TOP_ACR_CNTL_STAT, data32);
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
if (rx.chip_id == CHIP_ID_TL1) {
data32 = 0;
data32 |= 0 << 2;/*meas_mode*/
data32 |= 1 << 1;/*enable*/
@@ -2093,12 +2080,12 @@ void snps_phyg3_init(void)
hdmirx_wr_dwc(DWC_SNPS_PHYG3_CTRL, data32);
data32 = 0;
data32 |= phy_lock_thres << 10;
data32 |= 6 << 10;
data32 |= 1 << 9;
data32 |= ((phy_cfg_clk * 4) / 1000);
data32 |= ((24000 * 4) / 1000);
hdmirx_wr_phy(PHY_CMU_CONFIG, data32);
hdmirx_wr_phy(PHY_VOLTAGE_LEVEL, eq_ref_voltage);
hdmirx_wr_phy(PHY_VOLTAGE_LEVEL, 0x1ea);
data32 = 0;
data32 |= 0 << 15;
@@ -2148,7 +2135,7 @@ void snps_phyg3_init(void)
/* clear clkrate cfg */
hdmirx_wr_bits_phy(PHY_CDR_CTRL_CNT, CLK_RATE_BIT, 0);
/*last_clk_rate = 0;*/
rx.physts.clk_rate = 0;
rx.phy.clk_rate = 0;
/* enable all ports's termination */
data32 = 0;
data32 |= 1 << 8;
@@ -2170,24 +2157,12 @@ void snps_phyg3_init(void)
*/
void hdmirx_phy_init(void)
{
uint32_t data32;
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
/* give default value */
data32 = 0;
data32 |= rx.port << 2;
hdmirx_wr_dwc(DWC_SNPS_PHYG3_CTRL, data32);
if (rx.physts.cable_clk > 0)
aml_phy_bw_switch(rx.physts.cable_clk,
rx.physts.clk_rate);
else
aml_phy_bw_switch(PHY_DEFAULT_FRQ, 0);
} else {
/* uint32_t data32; */
/* uint32_t cur_cable_clk; */
if (rx.chip_id == CHIP_ID_TL1)
aml_phy_bw_switch();
else
snps_phyg3_init();
}
rx_pr("%s Done!\n", __func__);
}
/*
@@ -2201,12 +2176,13 @@ bool rx_clkrate_monitor(void)
bool changed = false;
int i;
int error = 0;
int cur_cable_clk;
uint32_t clk_diff;
uint32_t cur_phy_bw;
clk_rate = rx_get_scdc_clkrate_sts();
if (clk_rate != rx.physts.clk_rate) {
if (is_clk_stable()) {
rx.phy.cable_clk = rx_measure_clock(MEASURE_CLK_CABLE);
rx.phy.phy_bw = aml_cable_clk_band(rx.phy.cable_clk, clk_rate);
}
if (clk_rate != rx.phy.clk_rate) {
changed = true;
if (rx.chip_id != CHIP_ID_TL1) {
for (i = 0; i < 3; i++) {
@@ -2216,32 +2192,35 @@ bool rx_clkrate_monitor(void)
if (error == 0)
break;
}
} else {
aml_phy_bw_switch();
}
if (log_level & VIDEO_LOG)
rx_pr("clk_rate:%d, last_clk_rate: %d\n",
clk_rate, rx.physts.clk_rate);
rx.physts.clk_rate = clk_rate;
clk_rate, rx.phy.clk_rate);
rx.phy.clk_rate = clk_rate;
}
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
#if 0
if (rx.chip_id == CHIP_ID_TL1) {
cur_cable_clk = rx_measure_clock(MEASURE_CLK_CABLE);
clk_diff = diff(rx.physts.cable_clk, cur_cable_clk);
clk_diff = diff(rx.phy.cable_clk, cur_cable_clk);
/*clk_rate = rx_get_scdc_clkrate_sts();*/
cur_phy_bw = aml_cable_clk_band(cur_cable_clk, clk_rate);
if ((rx.cur_5v_sts) && ((rx.physts.phy_bw != cur_phy_bw) ||
if ((rx.cur_5v_sts) && ((rx.phy.phy_bw != cur_phy_bw) ||
changed || (clk_diff > (1000*KHz)))) {
changed = true;
aml_phy_bw_switch(cur_cable_clk, clk_rate);
aml_phy_bw_switch();
udelay(50);/*wait pll lock*/
rx_pr("phy clk chg:cabclk:%d,%d,rate:%d,lock:%d\n",
cur_cable_clk, rx.physts.cable_clk,
cur_cable_clk, rx.phy.cable_clk,
clk_rate, aml_phy_pll_lock());
rx.physts.cable_clk = cur_cable_clk;
rx.physts.clk_rate = clk_rate;
rx.physts.phy_bw = cur_phy_bw;
rx.phy.cable_clk = cur_cable_clk;
rx.phy.clk_rate = clk_rate;
rx.phy.phy_bw = cur_phy_bw;
}
}
#endif
if (changed) {
if (rx.state >= FSM_WAIT_CLK_STABLE)
rx.state = FSM_WAIT_CLK_STABLE;
@@ -2353,6 +2332,8 @@ void hdmirx_hw_config(void)
hdmirx_20_init();
DWC_init();
hdmirx_irq_hdcp_enable(true);
if (rx.chip_id == CHIP_ID_TL1)
aml_phy_switch_port();
hdmirx_phy_init();
hdmirx_wr_top(TOP_INTR_MASKN, top_intr_maskn_value);
rx_pr("%s %d Done!\n", __func__, rx.port);
@@ -2383,6 +2364,8 @@ void hdmirx_hw_probe(void)
packet_init();
if (rx.chip_id != CHIP_ID_TXHD)
hdmirx_20_init();
if (rx.chip_id == CHIP_ID_TL1)
aml_phy_switch_port();
hdmirx_phy_init();
hdmirx_wr_top(TOP_PORT_SEL, 0x10);
hdmirx_wr_top(TOP_INTR_STAT_CLR, ~0);
@@ -2467,7 +2450,7 @@ void rx_aud_pll_ctl(bool en)
int tmp = 0;
/*unsigned int od, od2;*/
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
if (rx.chip_id == CHIP_ID_TL1) {
if (en) {
/* AUD_CLK=N/CTS*TMDS_CLK */
/* bandgap enable */
@@ -2480,7 +2463,7 @@ void rx_aud_pll_ctl(bool en)
tmp |= 2 << 2; /* 0:tmds_clk 1:ref_clk 2:mpll_clk */
wr_reg_hhi(HHI_AUD_PLL_CNTL2, tmp);
/* cntl3 2:0 000=1*cts 001=2*cts 010=4*cts 011=8*cts */
wr_reg_hhi(HHI_AUD_PLL_CNTL3, rx.physts.aud_div);
wr_reg_hhi(HHI_AUD_PLL_CNTL3, rx.phy.aud_div);
#else
/* use tmds clk */
tmp = 0;
@@ -2722,10 +2705,10 @@ int rx_get_clock(enum measure_clk_top_e clk_src)
if (clk_src == TOP_HDMI_TMDSCLK)
tmp_data = hdmirx_rd_top(TOP_METER_HDMI_STAT);
else if (clk_src == TOP_HDMI_CABLECLK) {
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1)
if (rx.chip_id == CHIP_ID_TL1)
tmp_data = hdmirx_rd_top(TOP_METER_CABLE_STAT);
} else if (clk_src == TOP_HDMI_AUDIOCLK) {
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
if (rx.chip_id == CHIP_ID_TL1) {
/*get audio clk*/
tmp_data = hdmirx_rd_top(TOP_AUDMEAS_REF_CYCLES_STAT0);
tmp_data2 = hdmirx_rd_top(TOP_AUDMEAS_REF_CYCLES_STAT1);
@@ -2847,12 +2830,12 @@ unsigned int rx_measure_clock(enum measure_clk_src_e clksrc)
*/
if (clksrc == MEASURE_CLK_CABLE) {
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
if (rx.chip_id == CHIP_ID_TL1) {
clock = meson_clk_measure(30);
/*clock = rx_get_clock(TOP_HDMI_CABLECLK);*/
}
} else if (clksrc == MEASURE_CLK_TMDS) {
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1)
if (rx.chip_id == CHIP_ID_TL1)
clock = meson_clk_measure(63);
else {
clock = meson_clk_measure(25);
@@ -2865,18 +2848,18 @@ unsigned int rx_measure_clock(enum measure_clk_src_e clksrc)
} else if (clksrc == MEASURE_CLK_PIXEL) {
clock = meson_clk_measure(29);
} else if (clksrc == MEASURE_CLK_AUD_PLL) {
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1)
if (rx.chip_id == CHIP_ID_TL1)
clock = meson_clk_measure(74);/*audio vid out*/
else
clock = meson_clk_measure(24);
} else if (clksrc == MEASURE_CLK_AUD_DIV) {
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1)
if (rx.chip_id == CHIP_ID_TL1)
clock = meson_clk_measure(67);/*apll_clk_audio*/
else
clock = meson_clk_measure(98);
} else if (clksrc == MEASURE_CLK_MPLL) {
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1)
if (rx.chip_id == CHIP_ID_TL1)
clock = meson_clk_measure(29);/*apll_clk_out_div*/
else
clock = meson_clk_measure(27);
@@ -3006,7 +2989,7 @@ void dump_reg(void)
i = i + 4;
}
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
if (rx.chip_id == CHIP_ID_TL1) {
for (i = 0x25; i <= 0x84;) {
rx_pr("[0x%-3x]", i);
rx_pr("0x%-8x", hdmirx_rd_top(i));
@@ -3018,7 +3001,7 @@ void dump_reg(void)
}
}
if (rx.hdmirxdev->data->chip_id < CHIP_ID_TL1) {
if (rx.chip_id < CHIP_ID_TL1) {
rx_pr("\n***PHY registers***\n");
rx_pr("[addr ] addr + 0x0,");
rx_pr("addr + 0x1,addr + 0x2,");
@@ -3033,7 +3016,7 @@ void dump_reg(void)
i = i + 4;
}
} else if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
} else if (rx.chip_id == CHIP_ID_TL1) {
/* dump phy register */
rx_pr("\n***AML PHY registers***\n");
for (i = HHI_HDMIRX_APLL_CNTL0;
@@ -3185,7 +3168,7 @@ int rx_get_aud_pll_err_sts(void)
uint32_t phy_pll_rate = (hdmirx_rd_phy(PHY_MAINFSM_STATUS1)>>9)&0x3;
uint32_t aud_pll_cntl = (rd_reg_hhi(HHI_AUD_PLL_CNTL6)>>28)&0x3;
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
if (rx.chip_id == CHIP_ID_TL1) {
/* need to do something ...*/
} else {
if (req_clk > PHY_REQUEST_CLK_MAX ||
@@ -3213,6 +3196,9 @@ uint32_t aml_cable_clk_band(uint32_t cableclk,
uint32_t bw;
uint32_t cab_clk = cableclk;
if (rx.chip_id != CHIP_ID_TL1)
return phy_frq_band_2;
/*rx_pr("cable clk=%d, clkrate=%d\n", cableclk, clkrate);*/
/* 1:40 */
if (clkrate)
@@ -3236,120 +3222,232 @@ uint32_t aml_cable_clk_band(uint32_t cableclk,
return bw;
}
/*
* phy data table
* CNTL:0 1 2 3
* DCHA:0 1 2
* DCHD:0 2 1
*/
uint32_t phy_data[][10] = {
{/*phy_frq_band_0*/
0x30037078, 0x00000080, 0x02218000, 0x00000010,
0x00000182, 0x2800c202, 0x010088a2,
0x002c714a, 0x00018000, 0x1e013130
},
{/*phy_frq_band_1*/
0x30037078, 0x00000080, 0x02218000, 0x00000010,
0x000002a2, 0x4800c202, 0x01009126,
0x002c714a, 0x00028000, 0x1e062620
},
{/*phy_frq_band_2 1.5G*/
0x30037078, 0x00000080, 0x02218000, 0x00000010,
0x000002a2, 0x4800c202, 0x01009126,
0x002c714a, 0x00018000, 0x1e062620
},
{/*phy_frq_band_3 3G*/
0x30037078, 0x00000080, 0x02218000, 0x00000010,
0x000002a2, 0x0800c202, 0x0100fc31,
0x002c714a, 0x00028000, 0x1e062620
},
{/*phy_frq_band_4 6G*/
0x30037078, 0x007f0080, 0x02218000, 0x00000010,
0x351842a2, 0x0700003c, 0x1d00cc31,
0x002c715a, 0x00018000, 0x1e064640
},
};
void aml_phy_init(uint32_t bw)
void aml_phy_switch_port(void)
{
uint32_t idx = bw;
uint32_t data32;
uint32_t term_value = 0x7;/*all terminal on*/
/* hdmirx_rd_top(TOP_HPD_PWR5V);*/
rx_pr("init phy port %d, bw:%d\n", rx.port, bw);
if (bw > phy_frq_band_4) {
rx_pr("err phy frq band\n");
idx = phy_frq_band_2;
}
/* enable terminal connect */
data32 = phy_data[idx][0]|(term_value & 0x7);
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32);/*35c*/
/* data channel and common block reset */
data32 |= 0xf << 7;
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32);/*35c*/
udelay(2);
/*rx_pr("MISC_CNTL0=0x%x\n", data32);*/
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL1, phy_data[idx][1]);/*360*/
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL2, phy_data[idx][2]);/*380*/
/* reset and select data port */
data32 = phy_data[idx][3];
data32 = 0x00000010;
data32 |= ((1 << rx.port) << 6);
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL3, data32);
/* release reset */
data32 |= (1 << 11);
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL3, data32);
/*rx_pr("MISC_CNTL3=0x%x\n", data32);*/
udelay(5);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL0, phy_data[idx][4]);/*388*/
wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL1, phy_data[idx][5]);/*38c*/
wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL2, phy_data[idx][6]);/*390*/
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL0, phy_data[idx][7]);/*394*/
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, phy_data[idx][8]);/*39c*/
data32 = phy_data[idx][9];
data32 = 0;
data32 |= rx.port << 2;
hdmirx_wr_dwc(DWC_SNPS_PHYG3_CTRL, data32);
}
static const uint32_t phy_misci[][4] = {
/* 0xd7 0xd8 0xe0 0xe1 */
{ /* 24~45M */
0x3003707f, 0x00400080, 0x02218000, 0x00000010,
},
{ /* 45~74.5M */
0x3003707f, 0x00400080, 0x02218000, 0x00000010,
},
{ /* 77~155M */
0x3003707f, 0x00000080, 0x02218000, 0x00000010,
},
{ /* 155~340M */
0x3003707f, 0x00000080, 0x02218000, 0x00000010,
},
{ /* 340~600M */
0x3003707f, 0x007f0080, 0x02218000, 0x00000010,
},
};
static const uint32_t phy_dcha[][3] = {
/* 0xe2 0xe3 0xe4 */
{ /* 24~45M */
0x00000180, 0x2400c202, 0x030088a2,
},
{ /* 45~74.5M */
0x00000180, 0x2400c202, 0x030088a2,
},
{ /* 77~155M */
0x000002a2, 0x4800c202, 0x01009126,
},
{ /* 155~340M */
0x000002a2, 0x0800c202, 0x0100fc31,
},
{ /* 340~600M */
0x000002a2, 0x0700003c, 0x1d00cc31,
},
};
/* short cable */
static const uint32_t phy_dchd_1[][3] = {
/* 0xe5 0xe6 0xe7 */
{ /* 24~45M */
0x002e712a, 0x1e062620, 0x00018000,
},
{ /* 45~74.5M */
0x002e712a, 0x1e062620, 0x00018000,
},
{ /* 77~155M */
0x002c714a, 0x1e062620, 0x00018000,
},
{ /* 155~340M */
0x002c714a, 0x1e062620, 0x00018000,
},
{ /* 340~600M */
0x002c715a, 0x1e064640, 0x00018000,
},
};
/* long cable */
static const uint32_t phy_dchd_2[][3] = {
/* 0xe5 0xe6 0xe7 */
{ /* 24~45M */
0x002e712a, 0x1e022220, 0x00018000,
},
{ /* 45~74.5M */
0x002e712a, 0x1e022220, 0x00018000,
},
{ /* 77~155M */
0x002c714a, 0x1e022220, 0x00018000,
},
{ /* 155~340M */
0x002c714a, 0x1e022220, 0x00018000,
},
{ /* 340~600M */
0x002c715a, 0x1e012030, 0x00018000,
},
};
void aml_phy_init(void)
{
uint32_t idx = rx.phy.phy_bw;
uint32_t data32;
data32 = phy_misci[idx][0];
/* terminal en */
data32 &= ~(disable_port_num & 0x07);
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32);
udelay(2);
/* data channel and common block reset */
data32 |= 0xf << 7;
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32);
udelay(2);
data32 = phy_misci[idx][1];
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL1, data32);
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL2, phy_misci[idx][2]);
/* reset and select data port */
data32 = phy_misci[idx][3];
data32 |= ((1 << rx.port) << 6);
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL3, data32);
/* release reset */
data32 |= (1 << 11);
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL3, data32);
udelay(5);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL0, phy_dcha[idx][0]);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL1, phy_dcha[idx][1]);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL2, phy_dcha[idx][2]);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL0, phy_dchd_1[idx][0]);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, phy_dchd_1[idx][2]);
data32 = phy_dchd_1[idx][1];
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, data32);/*398*/
udelay(5);
data32 |= 0x00400000;
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, data32);/*398*/
}
uint32_t eq_data[][4] = {
/*DCHD_CNTL gp0:2, 1 gp1:2, 1*/
{0x00028000, 0x1e022220, 0x00028000, 0x1e062620},/*bw0*/
{0x00028000, 0x1e022220, 0x00028000, 0x1e062620},/*bw1*/
{0x00028000, 0x1e022220, 0x00018000, 0x1e062620},/*bw2*/
{0x00028000, 0x1e022220, 0x00028000, 0x1e062620},/*bw3*/
{0x00018000, 0x1e064640, 0x00018000, 0x1e064640},/*bw4*/
};
void aml_eq_setting(uint32_t bw)
void aml_eq_setting(void)
{
static uint32_t cnt;
uint32_t data;
uint32_t idx = bw;
uint32_t data32 = 0;
uint32_t idx = rx.phy.phy_bw;
if (bw > phy_frq_band_4) {
rx_pr("err phy frq band\n");
idx = phy_frq_band_2;
if (find_best_eq) {
data32 = phy_dchd_1[idx][1] & (~(MSK(16, 4)));
data32 |= find_best_eq << 4;
} else if ((rx.phy.cablesel % 2) == 0)
data32 = phy_dchd_1[idx][1];
else if ((rx.phy.cablesel % 2) == 1) {
data32 = phy_dchd_2[idx][1];
rx_pr("longcable\n");
}
if (cnt & 0x01) {
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, eq_data[idx][0]);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, eq_data[idx][1]);
udelay(1);
data = eq_data[idx][1] | 0x00400000;
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, data);
} else {
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, eq_data[idx][2]);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, eq_data[idx][3]);
udelay(1);
data = eq_data[idx][3] | 0x00400000;
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, data);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, data32);
udelay(2);
data32 |= 0x00400000;
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, data32);
}
void rx_get_best_eq_setting(void)
{
uint32_t ch0, ch1, ch2;
static uint32_t err_sum;
static uint32_t time_cnt;
static uint32_t array_cnt;
if ((rx.chip_id != CHIP_ID_TL1) ||
(!find_best_eq))
return;
if ((find_best_eq >= 0x7777) ||
(array_cnt >= 255)) {
rx_pr("eq traversal completed.\n");
rx_pr("best eq value:%d\n", array_cnt);
if (array_cnt) {
do {
rx_pr("%x:\n", rx.phy.eq_data[array_cnt]);
} while (array_cnt--);
} else
rx_pr("%x:\n", rx.phy.eq_data[array_cnt]);
find_best_eq = 0;
array_cnt = 0;
return;
}
if (time_cnt == 0) {
aml_phy_init();
udelay(1);
wr_reg_hhi_bits(HHI_HDMIRX_PHY_DCHD_CNTL1,
MSK(16, 4),
find_best_eq);
udelay(2);
wr_reg_hhi_bits(HHI_HDMIRX_PHY_DCHD_CNTL1, _BIT(22), 1);
rx_pr("set eq:%x\n", find_best_eq);
err_sum = 0;
do {
find_best_eq++;
} while (((find_best_eq & 0xf) > 7) ||
(((find_best_eq >> 4) & 0xf) > 7) ||
(((find_best_eq >> 8) & 0xf) > 7) ||
(((find_best_eq >> 12) & 0xf) > 7));
}
time_cnt++;
if (time_cnt > 2) {
rx_get_error_cnt(&ch0, &ch1, &ch2);
err_sum += (ch0 + ch1 + ch2);
}
if (time_cnt > eq_try_cnt) {
time_cnt = 0;
if (err_sum < rx.phy.err_sum) {
rx.phy.err_sum = err_sum;
rx_pr("err_sum = %d\n", err_sum);
array_cnt = 0;
rx.phy.eq_data[array_cnt] = find_best_eq;
} else if ((err_sum == rx.phy.err_sum) ||
(err_sum == 0)) {
rx.phy.err_sum = err_sum;
array_cnt++;
rx_pr("array = %x\n", array_cnt);
rx.phy.eq_data[array_cnt] = find_best_eq;
}
//if (ch0 || ch1 || ch2)
//rx_pr("err cnt:%d,%d,%d\n", ch0, ch1, ch2); ;
}
cnt++;
}
/*
@@ -3367,49 +3465,19 @@ struct apll_param apll_tab[] = {
{pll_frq_null, 40, 1, 0x3, 8, 0x3, 8},
};
uint32_t aml_phy_pll_band(uint32_t cableclk,
uint32_t clkrate)
{
uint32_t bw;
uint32_t cab_clk = cableclk;
if (clkrate)
cab_clk = cableclk << 2;
/* 1:10 */
if (cab_clk < (35*MHz))
bw = pll_frq_band_0;
else if (cab_clk < (77*MHz))
bw = pll_frq_band_1;
else if (cab_clk < (155*MHz))
bw = pll_frq_band_2;
else if (cab_clk < (300*MHz))
bw = pll_frq_band_3;
else if (cab_clk < (600*MHz))
bw = pll_frq_band_4;
else {
bw = pll_frq_band_2;
rx_pr("phy err: bw clk=%d\n", cableclk);
}
return bw;
}
void aml_phy_pll_setting(uint32_t cable_clk, uint32_t clkrate)
void aml_phy_pll_setting(void)
{
uint32_t M, N;
uint32_t od, od_div;
uint32_t od2, od2_div;
uint32_t bw;
uint32_t bw = rx.phy.phy_bw;
uint32_t vco_clk;
uint32_t apll_out;
uint32_t aud_pll_out;
uint32_t data, data2;
uint32_t aud_div;
uint32_t cableclk = cable_clk / KHz;
uint32_t cableclk = rx.phy.cable_clk / KHz;
bw = aml_phy_pll_band(cable_clk, clkrate);
rx_pr("bw:%d, cableclk:%d\n", bw, cableclk);
od_div = apll_tab[bw].od_div;
od = apll_tab[bw].od;
M = apll_tab[bw].M;
@@ -3423,12 +3491,7 @@ void aml_phy_pll_setting(uint32_t cable_clk, uint32_t clkrate)
/*tmds clk out*/
apll_out = (vco_clk/od_div)/5;
/*rx_pr("M=%d,N=%d,od=%d,od_div=%d\n", M, N, od, od_div);*/
rx_pr("apll_out=%d, vco_clk=%d\n", apll_out, vco_clk);
/*rx_pr("od2=%d, od2_div=%d\n", od2, od2_div);*/
aud_pll_out = ((vco_clk/od2_div)/5);
rx_pr("aud pll out=%d\n", aud_pll_out);
/*cntl0 M <7:0> N<14:10>*/
data = 0x00090400 & 0xffff8300;
@@ -3437,8 +3500,6 @@ void aml_phy_pll_setting(uint32_t cable_clk, uint32_t clkrate)
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data|0x20000000);
udelay(2);
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data|0x30000000);
/*rx_pr("APLL_CNTL0:0x%x\n", rd_reg_hhi(HHI_HDMIRX_APLL_CNTL0));*/
rd_reg_hhi(HHI_HDMIRX_APLL_CNTL0);
udelay(50);
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL1, 0x00000000);
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL2, 0x00001118);
@@ -3451,14 +3512,10 @@ void aml_phy_pll_setting(uint32_t cable_clk, uint32_t clkrate)
udelay(2);
/*apll_vctrl_mon_en*/
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL4, data2|0x00800000);
/*rx_pr("APLL_CNTL4:0x%x\n", rd_reg_hhi(HHI_HDMIRX_APLL_CNTL4));*/
rd_reg_hhi(HHI_HDMIRX_APLL_CNTL4);
udelay(80);
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data|0x34000000);
udelay(2);
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data|0x14000000);
/*rx_pr("APLL_CNTL0:0x%x\n", rd_reg_hhi(HHI_HDMIRX_APLL_CNTL0));*/
rd_reg_hhi(HHI_HDMIRX_APLL_CNTL0);
udelay(60);
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL2, 0x00003018);
/* common block release reset */
@@ -3472,7 +3529,6 @@ void aml_phy_pll_setting(uint32_t cable_clk, uint32_t clkrate)
/*set audio pll divider*/
aud_div = aud_pll_out/apll_out;
/*rx_pr("aud div=%d\n", aud_div);*/
if (aud_div == 1)
data = 0;
else if (aud_div == 2)
@@ -3483,7 +3539,7 @@ void aml_phy_pll_setting(uint32_t cable_clk, uint32_t clkrate)
data = 3;
else if (aud_div == 16)
data = 4;
rx.physts.aud_div = data;
rx.phy.aud_div = data;
}
void aml_phy_pw_onoff(uint32_t onoff)
@@ -3504,7 +3560,7 @@ void aml_phy_pw_onoff(uint32_t onoff)
data &= ~(1 << 9);
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data);
} else {
aml_phy_init(phy_frq_band_2);
aml_phy_init();
/*tl1_apll_setting(apll_frq_band_2);*/
}
}
@@ -3512,18 +3568,13 @@ void aml_phy_pw_onoff(uint32_t onoff)
/*
* aml phy initial
*/
void aml_phy_bw_switch(uint32_t cableclk, uint32_t clkrate)
void aml_phy_bw_switch(void)
{
uint32_t bw;
if (cableclk == 0)
cableclk = PHY_DEFAULT_FRQ;
bw = aml_cable_clk_band(cableclk, clkrate);
aml_phy_init(bw);
aml_phy_init();
udelay(1);
aml_phy_pll_setting(cableclk, clkrate);
aml_phy_pll_setting();
udelay(1);
aml_eq_setting(bw);
aml_eq_setting();
}
unsigned int aml_phy_pll_lock(void)
@@ -3591,7 +3642,7 @@ void rx_emp_to_ddr_init(void)
{
unsigned int data;
if (rx.hdmirxdev->data->chip_id != CHIP_ID_TL1)
if (rx.chip_id != CHIP_ID_TL1)
return;
if (rx.empbuff.pg_addr) {
@@ -3752,7 +3803,7 @@ void rx_tmds_to_ddr_init(void)
unsigned int data, data2;
unsigned int i = 0;
if (rx.hdmirxdev->data->chip_id != CHIP_ID_TL1)
if (rx.chip_id != CHIP_ID_TL1)
return;
if (rx.empbuff.pg_addr) {

13
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h
View File

@@ -1096,11 +1096,13 @@ extern int aud_mute_sel;
extern int pdec_ists_en;
extern int pd_fifo_start_cnt;
extern int md_ists_en;
extern int eq_ref_voltage;
extern int aud_ch_map;
extern int hdcp14_key_mode;
extern int ignore_sscp_charerr;
extern int ignore_sscp_tmds;
extern int find_best_eq;
extern int eq_try_cnt;
extern void rx_get_best_eq_setting(void);
extern void wr_reg_hhi(unsigned int offset, unsigned int val);
extern void wr_reg_hhi_bits(unsigned int offset, unsigned int mask,
@@ -1261,16 +1263,15 @@ struct apll_param {
extern int rx_get_clock(enum measure_clk_top_e clk_src);
extern unsigned int clk_util_clk_msr(unsigned int clk_mux);
extern unsigned int rx_measure_clock(enum measure_clk_src_e clksrc);
extern void aml_phy_init(uint32_t bw);
extern void aml_phy_init(void);
extern void aml_phy_pw_onoff(uint32_t onoff);
extern uint32_t aml_cable_clk_band(uint32_t cableclk,
uint32_t clkrate);
extern uint32_t aml_phy_pll_band(uint32_t cableclk,
uint32_t clkrate);
extern void aml_phy_bw_switch(uint32_t cableclk, uint32_t clkrate);
extern void aml_phy_switch_port(void);
extern void aml_phy_bw_switch(void);
extern unsigned int aml_phy_pll_lock(void);
extern unsigned int aml_phy_tmds_valid(void);
extern void aml_eq_setting(uint32_t bw);
extern void aml_eq_setting(void);
extern void rx_emp_to_ddr_init(void);
extern void rx_emp_field_done_irq(void);
extern void rx_emp_status(void);

637
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c
View File

@@ -89,10 +89,8 @@ int it_content;
static int diff_pixel_th = 2;
static int diff_line_th = 10;
static int diff_frame_th = 40; /* (25hz-24hz)/2 = 50/100 */
#ifdef USE_NEW_FSM_METHODE
static int err_dbg_cnt;
static int err_dbg_cnt_max = 500;
#endif
int force_vic;
uint32_t fsm_log_en;
uint32_t err_chk_en;
@@ -109,7 +107,6 @@ module_param(auds_rcv_sts, int, 0664);
MODULE_PARM_DESC(auds_rcv_sts, "auds_rcv_sts");
static int audio_coding_type;
static int audio_channel_count;
int log_level = LOG_EN;/*| HDCP_LOG;*/
@@ -117,7 +114,7 @@ int log_level = LOG_EN;/*| HDCP_LOG;*/
static bool auto_switch_off; /* only for hardware test */
int clk_unstable_cnt;
static int clk_unstable_max = 200;
static int clk_unstable_max;
int clk_stable_cnt;
static int clk_stable_max = 3;
@@ -186,6 +183,7 @@ static int esm_recovery_mode = ESM_REC_MODE_TMDS;
module_param(esm_recovery_mode, int, 0664);
MODULE_PARM_DESC(esm_recovery_mode, "esm_recovery_mode");
int phy_retry_times = 1;
/* No need to judge frame rate while checking timing stable,as there are
* some out-spec sources whose framerate change a lot(e.g:59.7~60.16hz).
* Other brands of tv can support this,we also need to support.
@@ -206,24 +204,20 @@ static bool hdcp22_esm_reset2_enable;
int sm_pause;
int pre_port = 0xff;
static int hdcp_none_wait_max = 100;
/* for no signal after esd test issue, phy
* does't work, cable clock or PLL can't
* lock, need to do phy reset.
*/
static int esd_phy_rst_cnt;
static int esd_phy_rst_max = 2;
#ifndef USE_NEW_FSM_METHODE
int pll_unlock_check_times;
int pll_unlock_check_times_max = 5;
static bool enable_hpd_reset;
static int sig_unstable_reset_hpd_cnt;
static int sig_unstable_reset_hpd_max = 5;
static bool is_hdcp_source = true;
#endif
static int esd_phy_rst_max;
struct rx_s rx;
void hdmirx_init_params(void)
{
if (rx.chip_id == CHIP_ID_TL1) {
clk_unstable_max = 10;
esd_phy_rst_max = 200;
} else {
clk_unstable_max = 200;
esd_phy_rst_max = 2;
}
}
void rx_hpd_to_esm_handle(struct work_struct *work)
{
@@ -349,7 +343,7 @@ static int hdmi_rx_ctrl_irq_handler(void)
}
}
if (rx.hdmirxdev->data->chip_id != CHIP_ID_TL1) {
if (rx.chip_id != CHIP_ID_TL1) {
rx_top_intr_stat = hdmirx_rd_top(TOP_INTR_STAT);
if (rx_top_intr_stat & _BIT(31))
irq_need_clr = 1;
@@ -503,7 +497,7 @@ reisr:hdmirx_top_intr_stat = hdmirx_rd_top(TOP_INTR_STAT);
hdmirx_wr_top(TOP_INTR_STAT_CLR, hdmirx_top_intr_stat);
/* modify interrupt flow for isr loading */
/* top interrupt handler */
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
if (rx.chip_id == CHIP_ID_TL1) {
if (hdmirx_top_intr_stat & (1 << 29))
if (log_level & 0x100)
rx_pr("[isr] sqofclk_fall\n");
@@ -540,7 +534,7 @@ reisr:hdmirx_top_intr_stat = hdmirx_rd_top(TOP_INTR_STAT);
rx_pr("[isr] enc fall\n");
/* must clear ip interrupt quickly */
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
if (rx.chip_id == CHIP_ID_TL1) {
hdmirx_top_intr_stat &= 0x1;
} else {
hdmirx_top_intr_stat &= (~(1 << 30));
@@ -557,7 +551,7 @@ reisr:hdmirx_top_intr_stat = hdmirx_rd_top(TOP_INTR_STAT);
}
}
if (rx.hdmirxdev->data->chip_id != CHIP_ID_TL1) {
if (rx.chip_id != CHIP_ID_TL1) {
if (error == 1)
goto reisr;
}
@@ -583,7 +577,7 @@ static const uint32_t sr_tbl[][2] = {
{192000, 3000},
{0, 0}
};
#ifdef USE_NEW_FSM_METHODE
static bool check_real_sr_change(void)
{
uint8_t i;
@@ -605,35 +599,6 @@ static bool check_real_sr_change(void)
}
return ret;
}
#else
static uint32_t get_real_sample_rate(void)
{
int i;
/* note: if arc is missmatch with LUT, then return 0 */
uint32_t ret_sr = 0; /* rx.aud_info.arc; */
for (i = 0; sr_tbl[i][0] != 0; i++) {
if (abs(rx.aud_info.arc - sr_tbl[i][0]) < sr_tbl[i][1]) {
ret_sr = sr_tbl[i][0];
break;
}
ret_sr = 0;
}
return ret_sr;
}
static unsigned char is_sample_rate_change(int sample_rate_pre,
int sample_rate_cur)
{
unsigned char ret = 1;
if (ABS(sample_rate_pre - sample_rate_cur) <
AUD_SR_RANGE)
ret = 0;
return ret;
}
#endif
static unsigned char is_aud_ch_map_change(int pre, int cur)
{
@@ -1071,7 +1036,7 @@ static bool rx_is_timing_stable(void)
rx.cur.colordepth);
}
/*for aml phy, check error counter*/
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1 &&
if (rx.chip_id == CHIP_ID_TL1 &&
(stable_check_lvl & ERR_CNT_EN)) {
rx_get_error_cnt(&ch0, &ch1, &ch2);
if ((ch0 + ch1 + ch2) > max_err_cnt) {
@@ -1080,7 +1045,7 @@ static bool rx_is_timing_stable(void)
sig_stable_err_cnt = 0;
/*phy setting is fail, need reset phy*/
sig_unstable_cnt = sig_unstable_max;
rx.physts.cable_clk = 0;
rx.phy.cable_clk = 0;
}
ret = false;
}
@@ -1094,24 +1059,6 @@ static bool rx_is_timing_stable(void)
return ret;
}
#ifndef USE_NEW_FSM_METHODE
static bool is_hdcp_enc_stable(void)
{
bool ret = true;
if ((rx.pre.hdcp14_state != rx.cur.hdcp14_state) &&
(rx.pre.hdcp_type == 0) &&
(stable_check_lvl & HDCP_ENC_EN)) {
ret = false;
if (log_level & VIDEO_LOG)
rx_pr("hdcp_enc_state(%d=>%d)\n",
rx.pre.hdcp14_state,
rx.cur.hdcp14_state);
}
return ret;
}
#endif
static int get_timing_fmt(void)
{
int i;
@@ -1172,10 +1119,8 @@ static void signal_status_init(void)
rx.aud_sr_unstable_cnt = 0;
//rx_aud_pll_ctl(0);
rx_set_eq_run_state(E_EQ_START);
#ifdef USE_NEW_FSM_METHODE
rx.err_rec_mode = ERR_REC_EQ_RETRY;
rx.err_code = ERR_NONE;
#endif
rx_irq_en(false);
if (hdcp22_on) {
if (esm_recovery_mode == ESM_REC_MODE_TMDS)
@@ -1187,9 +1132,6 @@ static void signal_status_init(void)
/*if (hdcp22_on)*/
/*esm_set_stable(0);*/
rx.hdcp.hdcp_version = HDCP_VER_NONE;
#ifndef USE_NEW_FSM_METHODE
is_hdcp_source = true;
#endif
rx.skip = 0;
}
@@ -1200,7 +1142,6 @@ void packet_update(void)
rgb_quant_range = rx.cur.rgb_quant_range;
yuv_quant_range = rx.cur.yuv_quant_range;
it_content = rx.cur.it_content;
auds_rcv_sts = rx.aud_info.aud_packet_received;
audio_sample_rate = rx.aud_info.real_sr;
audio_coding_type = rx.aud_info.coding_type;
@@ -1270,7 +1211,7 @@ bool is_tmds_valid(void)
if (force_vic)
return true;
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1)
if (rx.chip_id == CHIP_ID_TL1)
return (aml_phy_tmds_valid() == 1) ? true : false;
else
return (rx_get_pll_lock_sts() == 1) ? true : false;
@@ -1299,30 +1240,9 @@ void esm_recovery(void)
hdcp22_esm_reset2 = 1;
}
#ifndef USE_NEW_FSM_METHODE
void rx_esm_exception_monitor(void)
{
int irq_status, exception;
irq_status = rx_hdcp22_rd_reg(HPI_REG_IRQ_STATUS);
if (irq_status & IRQ_STATUS_UPDATE_BIT) {
exception =
rx_hdcp22_rd_reg_bits(HPI_REG_EXCEPTION_STATUS,
EXCEPTION_CODE);
if (exception != rx.hdcp.hdcp22_exception) {
rx_pr("++++++hdcp22 state:%#x,vec:%#x\n",
rx_hdcp22_rd_reg(HPI_REG_EXCEPTION_STATUS),
exception);
rx.hdcp.hdcp22_exception = exception;
}
}
}
#endif
bool is_unnormal_format(uint8_t wait_cnt)
{
bool ret = false;
#ifdef USE_NEW_FSM_METHODE
if ((rx.pre.sw_vic == HDMI_UNSUPPORT) ||
(rx.pre.sw_vic == HDMI_UNKNOWN)) {
ret = true;
@@ -1367,29 +1287,6 @@ bool is_unnormal_format(uint8_t wait_cnt)
if (log_level & VIDEO_LOG)
rx_pr("unnormal_format wait cnt = %d\n",
wait_cnt-sig_stable_max);
#else
if ((rx.pre.sw_vic == HDMI_UNSUPPORT) ||
(rx.pre.sw_vic == HDMI_UNKNOWN)) {
if (wait_cnt < unnormal_wait_max)
ret = true;
if (log_level & VIDEO_LOG)
rx_pr("*unsupport*\n");
}
if (rx.pre.sw_dvi == 1) {
if (wait_cnt < unnormal_wait_max)
ret = true;
if (log_level & VIDEO_LOG)
rx_pr("*DVI*\n");
}
if ((rx.pre.hdcp14_state != 3) &&
(rx.pre.hdcp14_state != 0) &&
(rx.hdcp.hdcp_version == HDCP_VER_14)) {
if (wait_cnt < unnormal_wait_max)
ret = true;
if (log_level & VIDEO_LOG)
rx_pr("hdcp14 unfinished\n");
}
#endif
return ret;
}
@@ -1406,9 +1303,9 @@ void fsm_restart(void)
vic_check_en = true;
dvi_check_en = true;
rx.state = FSM_INIT;
rx.physts.cable_clk = 0;
rx.physts.pll_rate = 0;
rx.physts.phy_bw = 0;
rx.phy.cable_clk = 0;
rx.phy.pll_rate = 0;
rx.phy.phy_bw = 0;
rx_pr("force_fsm_init\n");
}
@@ -1712,8 +1609,6 @@ int rx_set_global_variable(const char *buf, int size)
return pr_var(packet_fifo_cfg, index);
if (set_pr_var(tmpbuf, pd_fifo_start_cnt, value, &index, ret))
return pr_var(pd_fifo_start_cnt, index);
if (set_pr_var(tmpbuf, eq_ref_voltage, value, &index, ret))
return pr_var(eq_ref_voltage, index);
if (set_pr_var(tmpbuf, hdcp22_on, value, &index, ret))
return pr_var(hdcp22_on, index);
if (set_pr_var(tmpbuf, dv_nopacket_timeout, value, &index, ret))
@@ -1744,12 +1639,6 @@ int rx_set_global_variable(const char *buf, int size)
return pr_var(skip_frame_cnt, index);
if (set_pr_var(tmpbuf, vdin_drop_frame_cnt, value, &index, ret))
return pr_var(vdin_drop_frame_cnt, index);
#ifndef USE_NEW_FSM_METHODE
if (set_pr_var(tmpbuf, enable_hpd_reset, value, &index, ret))
return pr_var(enable_hpd_reset, index);
if (set_pr_var(tmpbuf, sig_unstable_reset_hpd_max, value, &index, ret))
return pr_var(sig_unstable_reset_hpd_max, index);
#endif
if (set_pr_var(tmpbuf, atmos_edid_update_hpd_en, value, &index, ret))
return pr_var(atmos_edid_update_hpd_en, index);
if (set_pr_var(tmpbuf, suspend_pddq_sel, value, &index, ret))
@@ -1770,7 +1659,12 @@ int rx_set_global_variable(const char *buf, int size)
return pr_var(fsm_log_en, index);
if (set_pr_var(tmpbuf, err_chk_en, value, &index, ret))
return pr_var(err_chk_en, index);
if (set_pr_var(tmpbuf, phy_retry_times, value, &index, ret))
return pr_var(phy_retry_times, index);
if (set_pr_var(tmpbuf, find_best_eq, value, &index, ret))
return pr_var(find_best_eq, index);
if (set_pr_var(tmpbuf, eq_try_cnt, value, &index, ret))
return pr_var(eq_try_cnt, index);
return 0;
}
@@ -1847,7 +1741,6 @@ void rx_get_global_variable(const char *buf)
pr_var(pdec_ists_en, i++);
pr_var(packet_fifo_cfg, i++);
pr_var(pd_fifo_start_cnt, i++);
pr_var(eq_ref_voltage, i++);
pr_var(hdcp22_on, i++);
pr_var(dv_nopacket_timeout, i++);
pr_var(delay_ms_cnt, i++);
@@ -1863,10 +1756,6 @@ void rx_get_global_variable(const char *buf)
pr_var(new_hdr_lum, i++);
pr_var(skip_frame_cnt, i++);
pr_var(vdin_drop_frame_cnt, i++);
#ifndef USE_NEW_FSM_METHODE
pr_var(enable_hpd_reset, i++);
pr_var(sig_unstable_reset_hpd_max, i++);
#endif
pr_var(atmos_edid_update_hpd_en, i++);
pr_var(suspend_pddq_sel, i++);
pr_var(aud_ch_map, i++);
@@ -1877,6 +1766,9 @@ void rx_get_global_variable(const char *buf)
pr_var(ignore_sscp_tmds, i++);
pr_var(fsm_log_en, i++);
pr_var(err_chk_en, i++);
pr_var(phy_retry_times, i++);
pr_var(find_best_eq, i++);
pr_var(eq_try_cnt, i++);
}
void skip_frame(unsigned int cnt)
@@ -1885,7 +1777,7 @@ void skip_frame(unsigned int cnt)
rx.skip = (1000 * 100 / rx.pre.frame_rate / 10) + 1;
rx.skip = cnt * rx.skip;
}
rx_pr("rx.skip = %d", rx.skip);
rx_pr("rx.skip = %d\n", rx.skip);
}
void wait_ddc_idle(void)
@@ -2011,13 +1903,8 @@ void rx_5v_monitor(void)
rx.cur_5v_sts = (pwr_sts >> rx.port) & 1;
hotplug_wait_query();
if (rx.cur_5v_sts == 0) {
/*External_Mute(1);*/
#ifdef USE_NEW_FSM_METHODE
set_fsm_state(FSM_5V_LOST);
rx.err_code = ERR_5V_LOST;
#else
set_fsm_state(FSM_HPD_LOW);
#endif
vic_check_en = true;
dvi_check_en = true;
}
@@ -2032,7 +1919,7 @@ void rx_5v_monitor(void)
*/
void rx_monitor_error_cnt_start(void)
{
rx.physts.timestap = get_seconds();
rx.phy.timestap = get_seconds();
}
/*
@@ -2044,20 +1931,19 @@ void rx_monitor_error_counter(void)
ulong timestap;
uint32_t ch0, ch1, ch2;
if (rx.hdmirxdev->data->chip_id != CHIP_ID_TL1)
if (rx.chip_id != CHIP_ID_TL1)
return;
timestap = get_seconds();
if ((timestap - rx.physts.timestap) > 1) {
rx.physts.timestap = timestap;
if ((timestap - rx.phy.timestap) > 1) {
rx.phy.timestap = timestap;
rx_get_error_cnt(&ch0, &ch1, &ch2);
if (ch0 || ch1 || ch2)
rx_pr("err cnt:%d,%d,%d\n", ch0, ch1, ch2);
}
}
#ifdef USE_NEW_FSM_METHODE
void rx_err_monitor(void)
{
//static bool hdcp14_sts;
@@ -2079,15 +1965,19 @@ void rx_err_monitor(void)
break;
case ERR_CLK_UNSTABLE:
if (err_dbg_cnt == 0)
rx_pr("PHY_MAINFSM_STATUS1 = %x\n",
hdmirx_rd_phy(PHY_MAINFSM_STATUS1));
rx_pr("clk unstable = %d\n",
is_clk_stable());
break;
case ERR_PHY_UNLOCK:
if (err_dbg_cnt == 0)
rx_pr("EQ = %d-%d-%d\n",
eq_ch0.bestsetting,
eq_ch1.bestsetting,
eq_ch2.bestsetting);
if (err_dbg_cnt == 0) {
if (rx.chip_id != CHIP_ID_TL1)
rx_pr("EQ = %d-%d-%d\n",
eq_ch0.bestsetting,
eq_ch1.bestsetting,
eq_ch2.bestsetting);
else
rx_pr("PHY unlock\n");
}
break;
case ERR_DE_UNSTABLE:
if (err_dbg_cnt == 0)
@@ -2154,7 +2044,7 @@ void rx_main_state_machine(void)
break;
case FSM_INIT:
signal_status_init();
rx.physts.cable_clk = 0;
rx.phy.cable_clk = 0;
rx.state = FSM_HPD_HIGH;
break;
case FSM_HPD_HIGH:
@@ -2174,7 +2064,8 @@ void rx_main_state_machine(void)
downstream_hpd_flag = 0;
pre_port = rx.port;
rx_set_cur_hpd(1);
rx.physts.cable_clk = 0;
rx.phy.cable_clk = 0;
rx.phy.cablesel = 0;
set_scdc_cfg(0, 1);
/* rx.hdcp.hdcp_version = HDCP_VER_NONE; */
rx.state = FSM_WAIT_CLK_STABLE;
@@ -2186,11 +2077,7 @@ void rx_main_state_machine(void)
clk_unstable_cnt = 0;
}
if (++clk_stable_cnt > clk_stable_max) {
/* for tl1 no SW eq */
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1)
rx.state = FSM_SIG_UNSTABLE;/*no sw eq*/
else
rx.state = FSM_EQ_START;
rx.state = FSM_EQ_START;
clk_stable_cnt = 0;
rx.err_code = ERR_NONE;
}
@@ -2201,14 +2088,9 @@ void rx_main_state_machine(void)
break;
}
clk_unstable_cnt = 0;
/* do phy reset for ESD no signal issue.
* sometimes after phy reset, phy is
* still not work, need to do phy reset
* again. do reset twice at most.
*/
if (esd_phy_rst_cnt < esd_phy_rst_max) {
hdmirx_phy_init();
rx.physts.cable_clk = 0;
rx.phy.cable_clk = 0;
esd_phy_rst_cnt++;
}
rx.err_code = ERR_CLK_UNSTABLE;
@@ -2241,22 +2123,17 @@ void rx_main_state_machine(void)
}
if (rx.err_rec_mode == ERR_REC_EQ_RETRY) {
rx.state = FSM_WAIT_CLK_STABLE;
/* pll unlock after ESD test, phy does't
* work well, do phy reset twice at most.
*/
if (esd_phy_rst_cnt++ < esd_phy_rst_max) {
hdmirx_phy_init();
rx.physts.cable_clk = 0;
rx.phy.cablesel++;
rx.phy.cable_clk = 0;
} else
rx.err_rec_mode = ERR_REC_HPD_RST;
} else if (rx.err_rec_mode == ERR_REC_HPD_RST) {
rx_set_cur_hpd(0);
rx.physts.cable_clk = 0;
rx.phy.cable_clk = 0;
rx.state = FSM_HPD_HIGH;
rx.err_rec_mode = ERR_REC_END;
} else {
rx.state = FSM_WAIT_CLK_STABLE;
rx.err_code = ERR_PHY_UNLOCK;
rx.err_rec_mode = ERR_REC_EQ_RETRY;
}
rx_set_eq_run_state(E_EQ_START);
}
@@ -2337,15 +2214,15 @@ void rx_main_state_machine(void)
}
if (rx.err_rec_mode == ERR_REC_EQ_RETRY) {
rx.state = FSM_WAIT_CLK_STABLE;
rx.phy.cablesel++;
rx.err_rec_mode = ERR_REC_HPD_RST;
rx_set_eq_run_state(E_EQ_START);
} else if (rx.err_rec_mode == ERR_REC_HPD_RST) {
rx_set_cur_hpd(0);
rx.physts.cable_clk = 0;
rx.phy.cable_clk = 0;
rx.state = FSM_HPD_HIGH;
rx.err_rec_mode = ERR_REC_END;
} else
rx.err_code = ERR_DE_UNSTABLE;
rx.err_rec_mode = ERR_REC_EQ_RETRY;
}
}
break;
case FSM_SIG_READY:
@@ -2377,7 +2254,7 @@ void rx_main_state_machine(void)
rx.skip = 0;
rx.aud_sr_stable_cnt = 0;
rx.aud_sr_unstable_cnt = 0;
rx.physts.cable_clk = 0;
rx.phy.cable_clk = 0;
esd_phy_rst_cnt = 0;
if (hdcp22_on) {
esm_set_stable(false);
@@ -2428,7 +2305,7 @@ void rx_main_state_machine(void)
hdmirx_phy_init();
rx.state = FSM_WAIT_CLK_STABLE;
/*timing sw at same FRQ*/
rx.physts.cable_clk = 0;
rx.phy.cable_clk = 0;
/*rx.pre_state = FSM_SIG_READY;*/
rx_pr("reqclk err->wait_clk\n");
} else if (aud_sts == E_PLLRATE_CHG)
@@ -2460,354 +2337,6 @@ void rx_main_state_machine(void)
rx.pre_state = rx.state;
}
}
#else
void rx_main_state_machine(void)
{
int pre_sample_rate;
int aud_pll_sts;
int pre_auds_ch_alloc;
if (clk_debug)
rx_cable_clk_monitor();
if (sm_pause)
return;
if (log_level & VIDEO_LOG)
rx_esm_exception_monitor();/* only for debug */
switch (rx.state) {
case FSM_HPD_LOW:
/* set_scdc_cfg(1, 1); */
rx_set_cur_hpd(0);
rx_irq_en(false);
rx.state = FSM_INIT;
set_scdc_cfg(1, 0);
rx_pr("HPD_LOW\n");
break;
case FSM_INIT:
signal_status_init();
rx.state = FSM_HPD_HIGH;
rx.pre_state = FSM_INIT;
rx_pr("FSM_INIT->HPD_HIGH\n");
break;
case FSM_HPD_HIGH:
if (rx.cur_5v_sts == 0) {
rx.no_signal = true;
break;
}
hpd_wait_cnt++;
if (rx_get_cur_hpd_sts() == 0) {
if (edid_update_flag) {
if (hpd_wait_cnt <= hpd_wait_max*10)
break;
} else {
if (hpd_wait_cnt <= hpd_wait_max)
break;
}
}
hpd_wait_cnt = 0;
pre_port = rx.port;
rx_set_cur_hpd(1);
set_scdc_cfg(0, 1);
/* some box init hdcp authentication too early
* and it may make the hdcp_version error
*/
/* rx.hdcp.hdcp_version = HDCP_VER_NONE; */
rx.state = FSM_WAIT_CLK_STABLE;
rx_pr("HPD_HIGH->CLK_STABLE\n");
break;
case FSM_WAIT_CLK_STABLE:
if (rx_clkrate_monitor()) {
rx_pr("clk rate changed\n");
break;
}
if (is_clk_stable()) {
clk_unstable_cnt = 0;
if (clk_stable_cnt++ > clk_stable_max) {
rx.state = FSM_EQ_START;
rx_pr("WAIT_CLK_STABLE->EQ_INIT\n");
clk_stable_cnt = 0;
}
} else {
clk_stable_cnt = 0;
if (clk_unstable_cnt++ >= clk_unstable_max) {
rx.state = FSM_HPD_LOW;
pre_port = 0xfe;
rx_pr("WAIT_CLK_STABLE->HPD_LOW\n");
clk_unstable_cnt = 0;
}
}
break;
case FSM_EQ_START:
if (rx_clkrate_monitor()) {
rx.state = FSM_WAIT_CLK_STABLE;
rx_pr("clk rate changed\n");
break;
}
rx_eq_algorithm();
rx.state = FSM_WAIT_EQ_DONE;
break;
case FSM_WAIT_EQ_DONE:
if (rx_get_eq_run_state() == E_EQ_FINISH ||
rx_get_eq_run_state() == E_EQ_SAME)
rx.state = FSM_SIG_UNSTABLE;
break;
case FSM_SIG_UNSTABLE:
if (rx_clkrate_monitor()) {
rx.state = FSM_WAIT_CLK_STABLE;
pll_lock_cnt = 0;
pll_unlock_cnt = 0;
rx_pr("clk rate changed\n");
break;
}
if (log_level & VIDEO_LOG)
rx_pr("lock_cnt:%d,unlock_cnt:%d\n",
pll_lock_cnt, pll_unlock_cnt);
if (is_tmds_valid()) {
pll_unlock_cnt = 0;
if (pll_lock_cnt++ > pll_lock_max) {
rx.state = FSM_SIG_WAIT_STABLE;
rx_dwc_reset();
pll_lock_cnt = 0;
pll_unlock_check_times = 0;
rx_pr("UNSTABLE->WAIT_STABLE\n");
}
} else {
pll_lock_cnt = 0;
if (pll_unlock_cnt++ >= pll_unlock_max) {
if (pll_unlock_check_times++ >=
pll_unlock_check_times_max) {
pll_unlock_check_times = 0;
rx.state = FSM_HPD_LOW;
} else
rx.state = FSM_WAIT_CLK_STABLE;
pll_unlock_cnt = 0;
rx_set_eq_run_state(E_EQ_FAIL);
rx_pr("UNSTABLE->HPD_LOW\n");
}
}
break;
case FSM_SIG_WAIT_STABLE:
if (rx_clkrate_monitor()) {
rx.state = FSM_WAIT_CLK_STABLE;
dwc_rst_wait_cnt = 0;
rx_pr("clk rate changed\n");
break;
}
dwc_rst_wait_cnt++;
if (dwc_rst_wait_cnt < dwc_rst_wait_cnt_max)
break;
if ((edid_update_flag) &&
(dwc_rst_wait_cnt < edid_update_delay))
break;
edid_update_flag = 0;
dwc_rst_wait_cnt = 0;
rx.state = FSM_SIG_STABLE;
rx_pr("DWC_RST->FSM_SIG_STABLE\n");
break;
case FSM_SIG_STABLE:
if (rx_clkrate_monitor()) {
rx.state = FSM_WAIT_CLK_STABLE;
sig_stable_cnt = 0;
sig_unstable_cnt = 0;
rx_pr("clk rate changed\n");
break;
}
memcpy(&rx.pre, &rx.cur,
sizeof(struct rx_video_info));
rx_get_video_info();
if (rx_is_timing_stable() && is_hdcp_enc_stable()) {
if (sig_stable_cnt++ > sig_stable_max) {
get_timing_fmt();
if (is_unnormal_format(sig_stable_cnt))
break;
if (fmt_vic_abnormal() &&
(vic_check_en == true)) {
hdmirx_hw_config();
hdmi_rx_top_edid_update();
rx.state = FSM_HPD_LOW;
vic_check_en = false;
break;
}
sig_stable_cnt = 0;
sig_unstable_cnt = 0;
if (rx.pre.sw_dvi && dvi_check_en &&
(rx.hdcp.hdcp_version ==
HDCP_VER_NONE)) {
rx.state = FSM_HPD_LOW;
dvi_check_en = false;
break;
}
rx.skip = 0;
if ((rx.pre.hdcp14_state == 0) ||
(rx.pre.hdcp14_state == 2))
is_hdcp_source = false;
rx.state = FSM_SIG_READY;
rx.aud_sr_stable_cnt = 0;
rx.aud_sr_unstable_cnt = 0;
rx.no_signal = false;
memset(&rx.aud_info, 0,
sizeof(struct aud_info_s));
//rx_set_eq_run_state(E_EQ_PASS);
hdmirx_config_video();
rx_get_audinfo(&rx.aud_info);
hdmirx_config_audio();
hdmirx_audio_fifo_rst();
rx_pr("STABLE->READY\n");
if (log_level & VIDEO_LOG)
dump_state(RX_DUMP_VIDEO);
}
} else {
sig_stable_cnt = 0;
if (sig_unstable_cnt++ > sig_unstable_max) {
rx.state = FSM_WAIT_CLK_STABLE;
rx_set_eq_run_state(E_EQ_FAIL);
sig_stable_cnt = 0;
sig_unstable_cnt = 0;
if (enable_hpd_reset) {
sig_unstable_reset_hpd_cnt++;
if (sig_unstable_reset_hpd_cnt >=
sig_unstable_reset_hpd_max) {
rx.state = FSM_HPD_HIGH;
rx_set_cur_hpd(0);
sig_unstable_reset_hpd_cnt = 0;
rx_pr(
"unstable->HDMI5V_HIGH\n");
break;
}
}
rx_pr("STABLE->HPD_READY\n");
}
}
break;
case FSM_SIG_READY:
if (rx_clkrate_monitor()) {
rx.state = FSM_WAIT_CLK_STABLE;
sig_unready_cnt = 0;
rx_pr("clk rate changed\n");
break;
}
rx_get_video_info();
/* video info change */
if ((is_tmds_valid() == false) ||
(rx_is_timing_stable() == false)) {
skip_frame(skip_frame_cnt);
if (++sig_unready_cnt >= sig_unready_max) {
/*sig_lost_lock_cnt = 0;*/
sig_unready_cnt = 0;
audio_sample_rate = 0;
rx_aud_pll_ctl(0);
rx.hdcp.hdcp_version = HDCP_VER_NONE;
rx.state = FSM_WAIT_CLK_STABLE;
rx.pre_state = FSM_SIG_READY;
rx.skip = 0;
vic_check_en = true;
rx.aud_sr_stable_cnt = 0;
rx.aud_sr_unstable_cnt = 0;
if (hdcp22_on) {
esm_set_stable(false);
if (esm_recovery_mode ==
ESM_REC_MODE_RESET)
esm_set_reset(true);
/* else */
/* rx_esm_tmdsclk_en(false); */
}
memset(&rx.pre, 0,
sizeof(struct rx_video_info));
memset(&rx.vs_info_details,
0,
sizeof(struct vsi_info_s));
rx_pr("READY->wait_clk\n");
break;
}
} else {
if (sig_unready_cnt != 0) {
if (log_level & VIDEO_LOG)
rx_pr("sig_unready_cnt=%d\n",
sig_unready_cnt);
sig_unready_cnt = 0;
}
}
/* if (rx.no_signal == true) */
/* rx.no_signal = false; */
if (rx.skip > 0) {
rx.skip--;
if (log_level & VIDEO_LOG)
rx_pr("rc--%d\n", rx.skip);
}
if (rx.pre.sw_dvi == 1)
break;
pre_sample_rate = rx.aud_info.real_sr;
pre_auds_ch_alloc = rx.aud_info.auds_ch_alloc;
rx_get_audinfo(&rx.aud_info);
rx.aud_info.real_sr =
get_real_sample_rate();
if (is_sample_rate_change
(pre_sample_rate, rx.aud_info.real_sr) ||
is_aud_ch_map_change
(pre_auds_ch_alloc, rx.aud_info.auds_ch_alloc)) {
if (log_level & AUDIO_LOG)
dump_state(RX_DUMP_AUDIO);
rx.aud_sr_stable_cnt = 0;
break;
}
packet_update();
if (rx.aud_sr_stable_cnt < aud_sr_stb_max) {
rx.aud_sr_stable_cnt++;
break;
}
if (rx.aud_sr_stable_cnt == aud_sr_stb_max) {
dump_state(RX_DUMP_AUDIO);
rx_aud_pll_ctl(1);
if (is_afifo_error()) {
if (log_level & AUDIO_LOG)
rx_pr("afifo err\n");
}
hdmirx_config_audio();
hdmirx_audio_fifo_rst();
rx_pr("update audio\n");
rx_audio_pll_sw_update();
rx.aud_sr_stable_cnt++;
}
if (is_aud_pll_error()) {
rx.aud_sr_unstable_cnt++;
if (rx.aud_sr_unstable_cnt > aud_sr_stb_max) {
aud_pll_sts = rx_get_aud_pll_err_sts();
if (aud_pll_sts == E_REQUESTCLK_ERR) {
hdmirx_phy_init();
rx.state = FSM_WAIT_CLK_STABLE;
rx.pre_state = FSM_SIG_READY;
rx_pr("reqclk err->wait_clk\n");
} else if (aud_pll_sts == E_PLLRATE_CHG)
rx_aud_pll_ctl(1);
else if (aud_pll_sts == E_AUDCLK_ERR) {
rx_audio_bandgap_rst();
rx.aud_sr_stable_cnt = 0;
} else {
rx_acr_info_sw_update();
rx_audio_pll_sw_update();
if (log_level & AUDIO_LOG)
rx_pr("update audio-err\n");
}
rx.aud_sr_unstable_cnt = 0;
}
} else
rx.aud_sr_unstable_cnt = 0;
break;
default:
break;
}
}
#endif
unsigned int hdmirx_show_info(unsigned char *buf, int size)
{
@@ -2926,7 +2455,7 @@ static void dump_phy_status(void)
uint32_t val0, val1, val2;
rx_pr("[PHY info]\n");
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
if (rx.chip_id == CHIP_ID_TL1) {
rx_get_error_cnt(&val0, &val1, &val2);
rx_pr("err cnt- ch0: %d,ch1:%d ch2:%d\n", val0, val1, val2);
rx_pr("PLL_LCK_STS(tmds valid) = 0x%x\n",
@@ -3011,7 +2540,7 @@ static void dump_audio_status(void)
rx_pr(" CA=%u\n", a.auds_ch_alloc);
rx_pr("CTS=%d, N=%d,", a.cts, a.n);
rx_pr("acr clk=%d\n", a.arc);
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
if (rx.chip_id == CHIP_ID_TL1) {
rx_get_audio_N_CTS(&val0, &val1);
rx_pr("top CTS:%d, N:%d\n", val1, val0);
}
@@ -3058,12 +2587,18 @@ static void dump_hdcp_status(void)
hdmirx_rd_dwc(DWC_HDCP_BKSV0));
}
void dump_state(enum dumpinfo_e enable)
void dump_state(int enable)
{
rx_get_video_info();
if (enable & RX_DUMP_VIDEO) /* video info */
if (enable == RX_DUMP_VIDEO) /* video info */
dump_video_status();
else if (enable & RX_DUMP_AUDIO) /* audio info */
else if (enable & RX_DUMP_ALL) {
dump_clk_status();
dump_phy_status();
dump_video_status();
dump_audio_status();
dump_hdcp_status();
} else if (enable & RX_DUMP_AUDIO) /* audio info */
dump_audio_status();
else if (enable & RX_DUMP_HDCP) /* hdcp info */
dump_hdcp_status();
@@ -3071,13 +2606,8 @@ void dump_state(enum dumpinfo_e enable)
dump_phy_status();
else if (enable & RX_DUMP_CLK) /* clk src info */
dump_clk_status();
else {
dump_clk_status();
dump_phy_status();
else
dump_video_status();
dump_audio_status();
dump_hdcp_status();
}
}
void rx_debug_help(void)
@@ -3255,10 +2785,11 @@ int hdmirx_debug(const char *buf, int size)
rx_pr("set pkt cnt:0x%x\n", value);
rx.empbuff.tmdspktcnt = value;
} else if (strncmp(input[0], "phyinit", 7) == 0) {
aml_phy_bw_switch(rx_get_clock(TOP_HDMI_CABLECLK),
rx_get_scdc_clkrate_sts());
aml_phy_bw_switch();
} else if (strncmp(input[0], "phyeq", 5) == 0) {
aml_eq_setting(rx.physts.phy_bw);
//aml_eq_setting();
find_best_eq = 0x1111;
rx.phy.err_sum = 0xffffff;
} else if (strncmp(tmpbuf, "audio", 5) == 0) {
hdmirx_audio_fifo_rst();
}
@@ -3276,19 +2807,15 @@ void hdmirx_timer_handler(unsigned long arg)
rx_nosig_monitor();
if (!hdmirx_repeat_support() || !rx.firm_change) {
if (!sm_pause) {
#ifdef USE_NEW_FSM_METHODE
rx_clkrate_monitor();
#endif
rx_main_state_machine();
}
rx_pkt_check_content();
#ifdef USE_NEW_FSM_METHODE
rx_err_monitor();
#endif
#ifdef K_TEST_CHK_ERR_CNT
if (err_chk_en || (rx.state != FSM_SIG_READY))
if (err_chk_en)
rx_monitor_error_counter();
rx_get_best_eq_setting();
#endif
}
}

10
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.h
View File

@@ -37,7 +37,6 @@
#define PHY_REQUEST_CLK_MIN 170000000
#define PHY_REQUEST_CLK_MAX 370000000
#define TIMER_STATE_CHECK (1*HZ/100)
#define USE_NEW_FSM_METHODE
struct freq_ref_s {
bool interlace;
@@ -105,12 +104,12 @@ enum aud_clk_err_e {
};
enum dumpinfo_e {
RX_DUMP_VIDEO = 0x01,
RX_DUMP_VIDEO = 0,
RX_DUMP_ALL = 1,
RX_DUMP_AUDIO = 0x02,
RX_DUMP_HDCP = 0x04,
RX_DUMP_PHY = 0x08,
RX_DUMP_CLK = 0x10,
RX_DUMP_ALL = 0x80,
RX_DUMP_CLK = 0x10
};
/* signal */
@@ -137,6 +136,7 @@ extern void rx_tmds_resource_allocate(struct device *dev);
extern void rx_emp_resource_allocate(struct device *dev);
extern void rx_emp_data_capture(void);
extern void rx_tmds_data_capture(void);
extern void dump_state(enum dumpinfo_e enable);
extern void dump_state(int enable);
extern void hdmirx_init_params(void);
#endif