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ice: Add E830 device IDs, MAC type and registers
[ Upstream commit ba1124f58afd37d9ff155d4ab7c9f209346aaed9 ] E830 is the 200G NIC family which uses the ice driver. Add specific E830 registers. Embed macros to use proper register based on (hw)->mac_type & name those macros to [ORIGINAL]_BY_MAC(hw). Registers only available on one of the macs will need to be explicitly referred to as E800_NAME instead of just NAME. PTP is not yet supported. Co-developed-by: Milena Olech <milena.olech@intel.com> Signed-off-by: Milena Olech <milena.olech@intel.com> Co-developed-by: Dan Nowlin <dan.nowlin@intel.com> Signed-off-by: Dan Nowlin <dan.nowlin@intel.com> Co-developed-by: Scott Taylor <scott.w.taylor@intel.com> Signed-off-by: Scott Taylor <scott.w.taylor@intel.com> Co-developed-by: Pawel Chmielewski <pawel.chmielewski@intel.com> Signed-off-by: Pawel Chmielewski <pawel.chmielewski@intel.com> Reviewed-by: Simon Horman <horms@kernel.org> Signed-off-by: Paul Greenwalt <paul.greenwalt@intel.com> Tested-by: Tony Brelinski <tony.brelinski@intel.com> Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> Link: https://lore.kernel.org/r/20231025214157.1222758-2-jacob.e.keller@intel.com Signed-off-by: Jakub Kicinski <kuba@kernel.org> Stable-dep-of: 79990cf5e7ad ("ice: Fix deinitializing VF in error path") Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Paul Greenwalt
committed by
Greg Kroah-Hartman
Greg Kroah-Hartman
parent
ab82f7a80b
commit
88f7ac6c4f
@@ -1,5 +1,5 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2018, Intel Corporation. */
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/* Copyright (c) 2018-2023, Intel Corporation. */
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#include "ice_common.h"
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#include "ice_sched.h"
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@@ -153,6 +153,12 @@ static int ice_set_mac_type(struct ice_hw *hw)
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case ICE_DEV_ID_E823L_SFP:
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hw->mac_type = ICE_MAC_GENERIC;
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break;
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case ICE_DEV_ID_E830_BACKPLANE:
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case ICE_DEV_ID_E830_QSFP56:
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case ICE_DEV_ID_E830_SFP:
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case ICE_DEV_ID_E830_SFP_DD:
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hw->mac_type = ICE_MAC_E830;
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break;
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default:
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hw->mac_type = ICE_MAC_UNKNOWN;
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break;
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@@ -684,8 +690,7 @@ static void
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ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,
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struct ice_aqc_set_mac_cfg *cmd)
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{
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u16 fc_thres_val, tx_timer_val;
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u32 val;
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u32 val, fc_thres_m;
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/* We read back the transmit timer and FC threshold value of
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* LFC. Thus, we will use index =
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@@ -694,19 +699,32 @@ ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,
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* Also, because we are operating on transmit timer and FC
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* threshold of LFC, we don't turn on any bit in tx_tmr_priority
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*/
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#define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
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#define E800_IDX_OF_LFC E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX
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#define E800_REFRESH_TMR E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR
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/* Retrieve the transmit timer */
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val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
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tx_timer_val = val &
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PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
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cmd->tx_tmr_value = cpu_to_le16(tx_timer_val);
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if (hw->mac_type == ICE_MAC_E830) {
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/* Retrieve the transmit timer */
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val = rd32(hw, E830_PRTMAC_CL01_PS_QNT);
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cmd->tx_tmr_value =
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le16_encode_bits(val, E830_PRTMAC_CL01_PS_QNT_CL0_M);
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/* Retrieve the FC threshold */
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val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
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fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M;
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/* Retrieve the fc threshold */
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val = rd32(hw, E830_PRTMAC_CL01_QNT_THR);
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fc_thres_m = E830_PRTMAC_CL01_QNT_THR_CL0_M;
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} else {
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/* Retrieve the transmit timer */
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val = rd32(hw,
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E800_PRTMAC_HSEC_CTL_TX_PS_QNT(E800_IDX_OF_LFC));
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cmd->tx_tmr_value =
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le16_encode_bits(val,
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E800_PRTMAC_HSEC_CTL_TX_PS_QNT_M);
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cmd->fc_refresh_threshold = cpu_to_le16(fc_thres_val);
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/* Retrieve the fc threshold */
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val = rd32(hw,
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E800_REFRESH_TMR(E800_IDX_OF_LFC));
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fc_thres_m = E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR_M;
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}
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cmd->fc_refresh_threshold = le16_encode_bits(val, fc_thres_m);
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}
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/**
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@@ -2389,16 +2407,21 @@ ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
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static void
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ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p)
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{
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u32 reg_val, val;
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u32 reg_val, gsize, bsize;
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reg_val = rd32(hw, GLQF_FD_SIZE);
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val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
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GLQF_FD_SIZE_FD_GSIZE_S;
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func_p->fd_fltr_guar =
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ice_get_num_per_func(hw, val);
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val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
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GLQF_FD_SIZE_FD_BSIZE_S;
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func_p->fd_fltr_best_effort = val;
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switch (hw->mac_type) {
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case ICE_MAC_E830:
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gsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_GSIZE_M, reg_val);
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bsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_BSIZE_M, reg_val);
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break;
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case ICE_MAC_E810:
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default:
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gsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_GSIZE_M, reg_val);
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bsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_BSIZE_M, reg_val);
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}
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func_p->fd_fltr_guar = ice_get_num_per_func(hw, gsize);
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func_p->fd_fltr_best_effort = bsize;
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ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n",
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func_p->fd_fltr_guar);
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@@ -1,5 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018, Intel Corporation. */
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/* Copyright (c) 2018-2023, Intel Corporation. */
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#ifndef _ICE_DEVIDS_H_
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#define _ICE_DEVIDS_H_
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@@ -16,6 +16,14 @@
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#define ICE_DEV_ID_E823L_1GBE 0x124F
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/* Intel(R) Ethernet Connection E823-L for QSFP */
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#define ICE_DEV_ID_E823L_QSFP 0x151D
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/* Intel(R) Ethernet Controller E830-C for backplane */
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#define ICE_DEV_ID_E830_BACKPLANE 0x12D1
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/* Intel(R) Ethernet Controller E830-C for QSFP */
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#define ICE_DEV_ID_E830_QSFP56 0x12D2
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/* Intel(R) Ethernet Controller E830-C for SFP */
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#define ICE_DEV_ID_E830_SFP 0x12D3
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/* Intel(R) Ethernet Controller E830-C for SFP-DD */
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#define ICE_DEV_ID_E830_SFP_DD 0x12D4
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/* Intel(R) Ethernet Controller E810-C for backplane */
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#define ICE_DEV_ID_E810C_BACKPLANE 0x1591
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/* Intel(R) Ethernet Controller E810-C for QSFP */
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@@ -1,5 +1,5 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (C) 2018-2020, Intel Corporation. */
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/* Copyright (C) 2018-2023, Intel Corporation. */
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/* flow director ethtool support for ice */
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@@ -540,16 +540,24 @@ int ice_fdir_num_avail_fltr(struct ice_hw *hw, struct ice_vsi *vsi)
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/* total guaranteed filters assigned to this VSI */
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num_guar = vsi->num_gfltr;
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/* minus the guaranteed filters programed by this VSI */
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num_guar -= (rd32(hw, VSIQF_FD_CNT(vsi_num)) &
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VSIQF_FD_CNT_FD_GCNT_M) >> VSIQF_FD_CNT_FD_GCNT_S;
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/* total global best effort filters */
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num_be = hw->func_caps.fd_fltr_best_effort;
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/* minus the global best effort filters programmed */
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num_be -= (rd32(hw, GLQF_FD_CNT) & GLQF_FD_CNT_FD_BCNT_M) >>
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GLQF_FD_CNT_FD_BCNT_S;
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/* Subtract the number of programmed filters from the global values */
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switch (hw->mac_type) {
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case ICE_MAC_E830:
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num_guar -= FIELD_GET(E830_VSIQF_FD_CNT_FD_GCNT_M,
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rd32(hw, VSIQF_FD_CNT(vsi_num)));
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num_be -= FIELD_GET(E830_GLQF_FD_CNT_FD_BCNT_M,
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rd32(hw, GLQF_FD_CNT));
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break;
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case ICE_MAC_E810:
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default:
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num_guar -= FIELD_GET(E800_VSIQF_FD_CNT_FD_GCNT_M,
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rd32(hw, VSIQF_FD_CNT(vsi_num)));
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num_be -= FIELD_GET(E800_GLQF_FD_CNT_FD_BCNT_M,
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rd32(hw, GLQF_FD_CNT));
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}
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return num_guar + num_be;
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}
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@@ -1,5 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018, Intel Corporation. */
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/* Copyright (c) 2018-2023, Intel Corporation. */
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/* Machine-generated file */
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@@ -284,11 +284,11 @@
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#define VPLAN_TX_QBASE_VFNUMQ_M ICE_M(0xFF, 16)
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#define VPLAN_TXQ_MAPENA(_VF) (0x00073800 + ((_VF) * 4))
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#define VPLAN_TXQ_MAPENA_TX_ENA_M BIT(0)
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#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(_i) (0x001E36E0 + ((_i) * 32))
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#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 8
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#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M ICE_M(0xFFFF, 0)
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#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3800 + ((_i) * 32))
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#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M ICE_M(0xFFFF, 0)
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#define E800_PRTMAC_HSEC_CTL_TX_PS_QNT(_i) (0x001E36E0 + ((_i) * 32))
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#define E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX 8
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#define E800_PRTMAC_HSEC_CTL_TX_PS_QNT_M GENMASK(15, 0)
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#define E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR(_i) (0x001E3800 + ((_i) * 32))
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#define E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR_M GENMASK(15, 0)
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#define GL_MDCK_TX_TDPU 0x00049348
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#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1)
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#define GL_MDET_RX 0x00294C00
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@@ -311,7 +311,11 @@
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#define GL_MDET_TX_PQM_MAL_TYPE_S 26
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#define GL_MDET_TX_PQM_MAL_TYPE_M ICE_M(0x1F, 26)
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#define GL_MDET_TX_PQM_VALID_M BIT(31)
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#define GL_MDET_TX_TCLAN 0x000FC068
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#define GL_MDET_TX_TCLAN_BY_MAC(hw) \
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((hw)->mac_type == ICE_MAC_E830 ? E830_GL_MDET_TX_TCLAN : \
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E800_GL_MDET_TX_TCLAN)
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#define E800_GL_MDET_TX_TCLAN 0x000FC068
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#define E830_GL_MDET_TX_TCLAN 0x000FCCC0
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#define GL_MDET_TX_TCLAN_QNUM_S 0
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#define GL_MDET_TX_TCLAN_QNUM_M ICE_M(0x7FFF, 0)
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#define GL_MDET_TX_TCLAN_VF_NUM_S 15
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@@ -325,7 +329,11 @@
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#define PF_MDET_RX_VALID_M BIT(0)
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#define PF_MDET_TX_PQM 0x002D2C80
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#define PF_MDET_TX_PQM_VALID_M BIT(0)
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#define PF_MDET_TX_TCLAN 0x000FC000
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#define PF_MDET_TX_TCLAN_BY_MAC(hw) \
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((hw)->mac_type == ICE_MAC_E830 ? E830_PF_MDET_TX_TCLAN : \
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E800_PF_MDET_TX_TCLAN)
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#define E800_PF_MDET_TX_TCLAN 0x000FC000
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#define E830_PF_MDET_TX_TCLAN 0x000FCC00
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#define PF_MDET_TX_TCLAN_VALID_M BIT(0)
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#define VP_MDET_RX(_VF) (0x00294400 + ((_VF) * 4))
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#define VP_MDET_RX_VALID_M BIT(0)
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@@ -335,6 +343,8 @@
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#define VP_MDET_TX_TCLAN_VALID_M BIT(0)
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#define VP_MDET_TX_TDPU(_VF) (0x00040000 + ((_VF) * 4))
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#define VP_MDET_TX_TDPU_VALID_M BIT(0)
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#define E800_GL_MNG_FWSM_FW_MODES_M GENMASK(2, 0)
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#define E830_GL_MNG_FWSM_FW_MODES_M GENMASK(1, 0)
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#define GL_MNG_FWSM 0x000B6134
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#define GL_MNG_FWSM_FW_LOADING_M BIT(30)
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#define GLNVM_FLA 0x000B6108
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@@ -363,13 +373,18 @@
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#define GL_PWR_MODE_CTL_CAR_MAX_BW_S 30
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#define GL_PWR_MODE_CTL_CAR_MAX_BW_M ICE_M(0x3, 30)
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#define GLQF_FD_CNT 0x00460018
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#define E800_GLQF_FD_CNT_FD_GCNT_M GENMASK(14, 0)
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#define E830_GLQF_FD_CNT_FD_GCNT_M GENMASK(15, 0)
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#define GLQF_FD_CNT_FD_BCNT_S 16
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#define GLQF_FD_CNT_FD_BCNT_M ICE_M(0x7FFF, 16)
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#define E800_GLQF_FD_CNT_FD_BCNT_M GENMASK(30, 16)
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#define E830_GLQF_FD_CNT_FD_BCNT_M GENMASK(31, 16)
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#define GLQF_FD_SIZE 0x00460010
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#define GLQF_FD_SIZE_FD_GSIZE_S 0
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#define GLQF_FD_SIZE_FD_GSIZE_M ICE_M(0x7FFF, 0)
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#define E800_GLQF_FD_SIZE_FD_GSIZE_M GENMASK(14, 0)
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#define E830_GLQF_FD_SIZE_FD_GSIZE_M GENMASK(15, 0)
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#define GLQF_FD_SIZE_FD_BSIZE_S 16
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#define GLQF_FD_SIZE_FD_BSIZE_M ICE_M(0x7FFF, 16)
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#define E800_GLQF_FD_SIZE_FD_BSIZE_M GENMASK(30, 16)
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#define E830_GLQF_FD_SIZE_FD_BSIZE_M GENMASK(31, 16)
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#define GLQF_FDINSET(_i, _j) (0x00412000 + ((_i) * 4 + (_j) * 512))
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#define GLQF_FDMASK(_i) (0x00410800 + ((_i) * 4))
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#define GLQF_FDMASK_MAX_INDEX 31
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@@ -388,6 +403,10 @@
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#define GLQF_HMASK_SEL(_i) (0x00410000 + ((_i) * 4))
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#define GLQF_HMASK_SEL_MAX_INDEX 127
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#define GLQF_HMASK_SEL_MASK_SEL_S 0
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#define E800_PFQF_FD_CNT_FD_GCNT_M GENMASK(14, 0)
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#define E830_PFQF_FD_CNT_FD_GCNT_M GENMASK(15, 0)
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#define E800_PFQF_FD_CNT_FD_BCNT_M GENMASK(30, 16)
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#define E830_PFQF_FD_CNT_FD_BCNT_M GENMASK(31, 16)
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#define PFQF_FD_ENA 0x0043A000
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#define PFQF_FD_ENA_FD_ENA_M BIT(0)
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#define PFQF_FD_SIZE 0x00460100
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@@ -478,6 +497,7 @@
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#define GLTSYN_SYNC_DLAY 0x00088818
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#define GLTSYN_TGT_H_0(_i) (0x00088930 + ((_i) * 4))
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#define GLTSYN_TGT_L_0(_i) (0x00088928 + ((_i) * 4))
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#define GLTSYN_TIME_0(_i) (0x000888C8 + ((_i) * 4))
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#define GLTSYN_TIME_H(_i) (0x000888D8 + ((_i) * 4))
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#define GLTSYN_TIME_L(_i) (0x000888D0 + ((_i) * 4))
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#define PFHH_SEM 0x000A4200 /* Reset Source: PFR */
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@@ -486,9 +506,11 @@
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#define PFTSYN_SEM_BUSY_M BIT(0)
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#define VSIQF_FD_CNT(_VSI) (0x00464000 + ((_VSI) * 4))
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#define VSIQF_FD_CNT_FD_GCNT_S 0
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#define VSIQF_FD_CNT_FD_GCNT_M ICE_M(0x3FFF, 0)
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#define E800_VSIQF_FD_CNT_FD_GCNT_M GENMASK(13, 0)
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#define E830_VSIQF_FD_CNT_FD_GCNT_M GENMASK(15, 0)
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#define VSIQF_FD_CNT_FD_BCNT_S 16
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#define VSIQF_FD_CNT_FD_BCNT_M ICE_M(0x3FFF, 16)
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#define E800_VSIQF_FD_CNT_FD_BCNT_M GENMASK(29, 16)
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#define E830_VSIQF_FD_CNT_FD_BCNT_M GENMASK(31, 16)
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#define VSIQF_FD_SIZE(_VSI) (0x00462000 + ((_VSI) * 4))
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#define VSIQF_HKEY_MAX_INDEX 12
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#define PFPM_APM 0x000B8080
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@@ -500,6 +522,10 @@
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#define PFPM_WUS_MAG_M BIT(1)
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#define PFPM_WUS_MNG_M BIT(3)
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#define PFPM_WUS_FW_RST_WK_M BIT(31)
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#define E830_PRTMAC_CL01_PS_QNT 0x001E32A0
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#define E830_PRTMAC_CL01_PS_QNT_CL0_M GENMASK(15, 0)
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#define E830_PRTMAC_CL01_QNT_THR 0x001E3320
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#define E830_PRTMAC_CL01_QNT_THR_CL0_M GENMASK(15, 0)
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#define VFINT_DYN_CTLN(_i) (0x00003800 + ((_i) * 4))
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#define VFINT_DYN_CTLN_CLEARPBA_M BIT(1)
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@@ -1,5 +1,5 @@
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||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/* Copyright (c) 2018, Intel Corporation. */
|
||||
/* Copyright (c) 2018-2023, Intel Corporation. */
|
||||
|
||||
/* Intel(R) Ethernet Connection E800 Series Linux Driver */
|
||||
|
||||
@@ -1748,7 +1748,7 @@ static void ice_handle_mdd_event(struct ice_pf *pf)
|
||||
wr32(hw, GL_MDET_TX_PQM, 0xffffffff);
|
||||
}
|
||||
|
||||
reg = rd32(hw, GL_MDET_TX_TCLAN);
|
||||
reg = rd32(hw, GL_MDET_TX_TCLAN_BY_MAC(hw));
|
||||
if (reg & GL_MDET_TX_TCLAN_VALID_M) {
|
||||
u8 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
|
||||
GL_MDET_TX_TCLAN_PF_NUM_S;
|
||||
@@ -1762,7 +1762,7 @@ static void ice_handle_mdd_event(struct ice_pf *pf)
|
||||
if (netif_msg_tx_err(pf))
|
||||
dev_info(dev, "Malicious Driver Detection event %d on TX queue %d PF# %d VF# %d\n",
|
||||
event, queue, pf_num, vf_num);
|
||||
wr32(hw, GL_MDET_TX_TCLAN, 0xffffffff);
|
||||
wr32(hw, GL_MDET_TX_TCLAN_BY_MAC(hw), U32_MAX);
|
||||
}
|
||||
|
||||
reg = rd32(hw, GL_MDET_RX);
|
||||
@@ -1790,9 +1790,9 @@ static void ice_handle_mdd_event(struct ice_pf *pf)
|
||||
dev_info(dev, "Malicious Driver Detection event TX_PQM detected on PF\n");
|
||||
}
|
||||
|
||||
reg = rd32(hw, PF_MDET_TX_TCLAN);
|
||||
reg = rd32(hw, PF_MDET_TX_TCLAN_BY_MAC(hw));
|
||||
if (reg & PF_MDET_TX_TCLAN_VALID_M) {
|
||||
wr32(hw, PF_MDET_TX_TCLAN, 0xFFFF);
|
||||
wr32(hw, PF_MDET_TX_TCLAN_BY_MAC(hw), 0xffff);
|
||||
if (netif_msg_tx_err(pf))
|
||||
dev_info(dev, "Malicious Driver Detection event TX_TCLAN detected on PF\n");
|
||||
}
|
||||
@@ -3873,7 +3873,8 @@ static void ice_set_pf_caps(struct ice_pf *pf)
|
||||
}
|
||||
|
||||
clear_bit(ICE_FLAG_PTP_SUPPORTED, pf->flags);
|
||||
if (func_caps->common_cap.ieee_1588)
|
||||
if (func_caps->common_cap.ieee_1588 &&
|
||||
!(pf->hw.mac_type == ICE_MAC_E830))
|
||||
set_bit(ICE_FLAG_PTP_SUPPORTED, pf->flags);
|
||||
|
||||
pf->max_pf_txqs = func_caps->common_cap.num_txq;
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* Copyright (c) 2018, Intel Corporation. */
|
||||
/* Copyright (c) 2018-2023, Intel Corporation. */
|
||||
|
||||
#ifndef _ICE_TYPE_H_
|
||||
#define _ICE_TYPE_H_
|
||||
@@ -129,6 +129,7 @@ enum ice_set_fc_aq_failures {
|
||||
enum ice_mac_type {
|
||||
ICE_MAC_UNKNOWN = 0,
|
||||
ICE_MAC_E810,
|
||||
ICE_MAC_E830,
|
||||
ICE_MAC_GENERIC,
|
||||
};
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/* Copyright (C) 2021, Intel Corporation. */
|
||||
/* Copyright (C) 2021-2023, Intel Corporation. */
|
||||
|
||||
#include "ice.h"
|
||||
#include "ice_base.h"
|
||||
@@ -1421,8 +1421,8 @@ ice_vc_fdir_irq_handler(struct ice_vsi *ctrl_vsi,
|
||||
*/
|
||||
static void ice_vf_fdir_dump_info(struct ice_vf *vf)
|
||||
{
|
||||
u32 fd_size, fd_cnt, fd_size_g, fd_cnt_g, fd_size_b, fd_cnt_b;
|
||||
struct ice_vsi *vf_vsi;
|
||||
u32 fd_size, fd_cnt;
|
||||
struct device *dev;
|
||||
struct ice_pf *pf;
|
||||
struct ice_hw *hw;
|
||||
@@ -1441,12 +1441,25 @@ static void ice_vf_fdir_dump_info(struct ice_vf *vf)
|
||||
|
||||
fd_size = rd32(hw, VSIQF_FD_SIZE(vsi_num));
|
||||
fd_cnt = rd32(hw, VSIQF_FD_CNT(vsi_num));
|
||||
dev_dbg(dev, "VF %d: space allocated: guar:0x%x, be:0x%x, space consumed: guar:0x%x, be:0x%x\n",
|
||||
vf->vf_id,
|
||||
(fd_size & VSIQF_FD_CNT_FD_GCNT_M) >> VSIQF_FD_CNT_FD_GCNT_S,
|
||||
(fd_size & VSIQF_FD_CNT_FD_BCNT_M) >> VSIQF_FD_CNT_FD_BCNT_S,
|
||||
(fd_cnt & VSIQF_FD_CNT_FD_GCNT_M) >> VSIQF_FD_CNT_FD_GCNT_S,
|
||||
(fd_cnt & VSIQF_FD_CNT_FD_BCNT_M) >> VSIQF_FD_CNT_FD_BCNT_S);
|
||||
switch (hw->mac_type) {
|
||||
case ICE_MAC_E830:
|
||||
fd_size_g = FIELD_GET(E830_VSIQF_FD_CNT_FD_GCNT_M, fd_size);
|
||||
fd_size_b = FIELD_GET(E830_VSIQF_FD_CNT_FD_BCNT_M, fd_size);
|
||||
fd_cnt_g = FIELD_GET(E830_VSIQF_FD_CNT_FD_GCNT_M, fd_cnt);
|
||||
fd_cnt_b = FIELD_GET(E830_VSIQF_FD_CNT_FD_BCNT_M, fd_cnt);
|
||||
break;
|
||||
case ICE_MAC_E810:
|
||||
default:
|
||||
fd_size_g = FIELD_GET(E800_VSIQF_FD_CNT_FD_GCNT_M, fd_size);
|
||||
fd_size_b = FIELD_GET(E800_VSIQF_FD_CNT_FD_BCNT_M, fd_size);
|
||||
fd_cnt_g = FIELD_GET(E800_VSIQF_FD_CNT_FD_GCNT_M, fd_cnt);
|
||||
fd_cnt_b = FIELD_GET(E800_VSIQF_FD_CNT_FD_BCNT_M, fd_cnt);
|
||||
}
|
||||
|
||||
dev_dbg(dev, "VF %d: Size in the FD table: guaranteed:0x%x, best effort:0x%x\n",
|
||||
vf->vf_id, fd_size_g, fd_size_b);
|
||||
dev_dbg(dev, "VF %d: Filter counter in the FD table: guaranteed:0x%x, best effort:0x%x\n",
|
||||
vf->vf_id, fd_cnt_g, fd_cnt_b);
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
Reference in New Issue
Block a user