mirror of
https://github.com/hardkernel/linux.git
synced 2026-06-05 18:41:58 +09:00
Merge commit '9f27599976115c76a15c488938bde23527d49d5b'
* commit '9f27599976115c76a15c488938bde23527d49d5b': (22 commits) ARM: dts: rockchip: disable rv1103g battery ipc dvfs arm64: dts: rockchip: rk3588s-evb2-lp5: fix usb2.0-only video: rockchip: mpp: fix access null task issue ASoC: rockchip: pdm: Fix register access in probe ASoC: rockchip: i2s: Fix register access in probe PCI: rockchip: dw: fix compliance mode set mtd: spinand: Enable HWP_EN for skyhigh devices mtd: spinand: esmt: Support new device F50L2G41KA arm64: dts: rockchip: rk3528: Set default value with level2 for spi ARM: configs: add rk3308bs_aarch32_mipi_display.config for rk3308bs support mipi display ARM: rockchip: rv1106: sleep: support hpmcu fast wakeup ARM: rockchip: Locate kernel at 0x00208000 for RV1106 when CONFIG_RV1106_HPMCU_FAST_WAKEUP=y ARM: configs: rockchip: add rv1106-wakeup.config ARM: rockchip: support RV1106_HPMCU_FAST_WAKEUP config arm64: dts: rockchip: rk3308-evb: add rgb display board media: rockchip: vicap fixes crop sync error mtd: spinand: xtx: Support new device XT26Q04DWSIGA mtd: spinand: gigadevcie: Add 3rd flash id for GD5F1GQ5RExxG mtd: spinand: xtx: Support new device XT26Q02DWSIGA and XT26Q01DWSIGA mtd: spinand: dosilicon: Support new device DS35Q1GD-IB ... Change-Id: I955f35e70228e9e91ca10d562293e6b6125f3584
This commit is contained in:
Tao Huang
@@ -161,6 +161,7 @@ ifeq ($(CONFIG_ROCKCHIP_THUNDER_BOOT),y)
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textofs-$(CONFIG_CPU_RV1106) := 0x00208000
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textofs-$(CONFIG_CPU_RV1126) := 0x00608000
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endif
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textofs-$(CONFIG_RV1106_HPMCU_FAST_WAKEUP) := 0x00208000
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# Machine directory name. This list is sorted alphanumerically
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# by CONFIG_* macro name.
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@@ -106,6 +106,11 @@
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status = "okay";
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};
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&cpu0 {
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/delete-property/ clocks;
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/delete-property/ operating-points-v2;
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};
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&csi2_dphy_hw {
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status = "okay";
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};
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@@ -106,6 +106,11 @@
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status = "okay";
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};
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&cpu0 {
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/delete-property/ clocks;
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/delete-property/ operating-points-v2;
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};
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&csi2_dphy_hw {
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status = "okay";
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};
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313
arch/arm/configs/rk3308bs_aarch32_mipi_display.config
Normal file
313
arch/arm/configs/rk3308bs_aarch32_mipi_display.config
Normal file
@@ -0,0 +1,313 @@
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CONFIG_BACKLIGHT_CLASS_DEVICE=y
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CONFIG_CMA=y
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CONFIG_DRM=y
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CONFIG_FB=y
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CONFIG_INPUT_TOUCHSCREEN=y
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CONFIG_KCMP=y
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CONFIG_MFD_RK618=y
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CONFIG_SYNC_FILE=y
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# CONFIG_BACKLIGHT_ADP8860 is not set
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||||
# CONFIG_BACKLIGHT_ADP8870 is not set
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# CONFIG_BACKLIGHT_ARCXCNN is not set
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# CONFIG_BACKLIGHT_BD6107 is not set
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# CONFIG_BACKLIGHT_GPIO is not set
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||||
# CONFIG_BACKLIGHT_KTD253 is not set
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# CONFIG_BACKLIGHT_LED is not set
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# CONFIG_BACKLIGHT_LM3630A is not set
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# CONFIG_BACKLIGHT_LM3639 is not set
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# CONFIG_BACKLIGHT_LP855X is not set
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# CONFIG_BACKLIGHT_LV5207LP is not set
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CONFIG_BACKLIGHT_PWM=y
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# CONFIG_BACKLIGHT_QCOM_WLED is not set
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CONFIG_CLK_RK618=y
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CONFIG_CMA_ALIGNMENT=8
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CONFIG_CMA_AREAS=7
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# CONFIG_CMA_DEBUG is not set
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# CONFIG_CMA_DEBUGFS is not set
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# CONFIG_CMA_INACTIVE is not set
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CONFIG_CMA_SIZE_MBYTES=16
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# CONFIG_CMA_SIZE_SEL_MAX is not set
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CONFIG_CMA_SIZE_SEL_MBYTES=y
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# CONFIG_CMA_SIZE_SEL_MIN is not set
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# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
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# CONFIG_CMA_SYSFS is not set
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CONFIG_COMMON_CLK_ROCKCHIP_REGMAP=y
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CONFIG_CONTIG_ALLOC=y
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# CONFIG_DMABUF_MOVE_NOTIFY is not set
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# CONFIG_DMABUF_SELFTESTS is not set
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# CONFIG_DMABUF_SYSFS_STATS is not set
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CONFIG_DMA_CMA=y
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# CONFIG_DMA_FENCE_TRACE is not set
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# CONFIG_DMA_PERNUMA_CMA is not set
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CONFIG_DMA_SHARED_BUFFER=y
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# CONFIG_DRM_ANALOGIX_ANX6345 is not set
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# CONFIG_DRM_ANALOGIX_ANX78XX is not set
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# CONFIG_DRM_ARCPGU is not set
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# CONFIG_DRM_ARMADA is not set
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CONFIG_DRM_BRIDGE=y
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# CONFIG_DRM_CDNS_DSI is not set
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# CONFIG_DRM_CDNS_MHDP8546 is not set
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# CONFIG_DRM_CHRONTEL_CH7033 is not set
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# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
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# CONFIG_DRM_DEBUG_MM is not set
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# CONFIG_DRM_DEBUG_SELFTEST is not set
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# CONFIG_DRM_DISPLAY_CONNECTOR is not set
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CONFIG_DRM_DP=y
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# CONFIG_DRM_DP_AUX_CHARDEV is not set
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# CONFIG_DRM_DP_CEC is not set
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CONFIG_DRM_EDID=y
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# CONFIG_DRM_ETNAVIV is not set
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# CONFIG_DRM_EXYNOS is not set
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CONFIG_DRM_FBDEV_EMULATION=y
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# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
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CONFIG_DRM_FBDEV_OVERALLOC=100
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# CONFIG_DRM_FSL_DCU is not set
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CONFIG_DRM_GEM_CMA_HELPER=y
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# CONFIG_DRM_HDLCD is not set
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# CONFIG_DRM_I2C_ADV7511 is not set
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# CONFIG_DRM_I2C_CH7006 is not set
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# CONFIG_DRM_I2C_NXP_TDA9950 is not set
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# CONFIG_DRM_I2C_NXP_TDA998X is not set
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# CONFIG_DRM_I2C_SIL164 is not set
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# CONFIG_DRM_IGNORE_IOTCL_PERMIT is not set
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# CONFIG_DRM_ITE_IT6161 is not set
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CONFIG_DRM_KMS_FB_HELPER=y
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CONFIG_DRM_KMS_HELPER=y
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# CONFIG_DRM_KOMEDA is not set
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# CONFIG_DRM_LEGACY is not set
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# CONFIG_DRM_LIMA is not set
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# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
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# CONFIG_DRM_LONTIUM_LT9611 is not set
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# CONFIG_DRM_LVDS_CODEC is not set
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# CONFIG_DRM_MALI_DISPLAY is not set
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# CONFIG_DRM_MAXIM_MAX96745 is not set
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# CONFIG_DRM_MAXIM_MAX96755F is not set
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# CONFIG_DRM_MCDE is not set
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# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
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CONFIG_DRM_MIPI_DSI=y
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# CONFIG_DRM_MXSFB is not set
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# CONFIG_DRM_NWL_MIPI_DSI is not set
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# CONFIG_DRM_NXP_PTN3460 is not set
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# CONFIG_DRM_OMAP is not set
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CONFIG_DRM_PANEL=y
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# CONFIG_DRM_PANEL_ARM_VERSATILE is not set
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# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set
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# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set
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# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set
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CONFIG_DRM_PANEL_BRIDGE=y
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# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set
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# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set
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# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set
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# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
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# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set
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# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set
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# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set
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# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set
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# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set
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# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set
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# CONFIG_DRM_PANEL_LG_LB035Q02 is not set
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# CONFIG_DRM_PANEL_LG_LG4573 is not set
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# CONFIG_DRM_PANEL_LVDS is not set
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# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set
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# CONFIG_DRM_PANEL_MAXIM_MAX96752F is not set
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# CONFIG_DRM_PANEL_MAXIM_MAX96772 is not set
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# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set
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# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set
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# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
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# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
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CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
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# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set
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# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set
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# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set
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# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set
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# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set
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# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set
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# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set
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# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
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# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set
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# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set
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# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set
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# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
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# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set
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# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
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# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
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# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set
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# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set
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# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set
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CONFIG_DRM_PANEL_SIMPLE=y
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# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set
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# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set
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# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
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# CONFIG_DRM_PANEL_SONY_ACX424AKP is not set
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# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set
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# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set
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# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set
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# CONFIG_DRM_PANEL_TPO_TPG110 is not set
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# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set
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# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set
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# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set
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# CONFIG_DRM_PANFROST is not set
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# CONFIG_DRM_PARADE_PS8622 is not set
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# CONFIG_DRM_PARADE_PS8640 is not set
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# CONFIG_DRM_PL111 is not set
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# CONFIG_DRM_RCAR_DW_HDMI is not set
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# CONFIG_DRM_RCAR_LVDS is not set
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# CONFIG_DRM_RK1000_TVE is not set
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CONFIG_DRM_ROCKCHIP=y
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CONFIG_DRM_ROCKCHIP_RK618=y
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# CONFIG_DRM_ROCKCHIP_VVOP is not set
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# CONFIG_DRM_ROHM_BU18XL82 is not set
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# CONFIG_DRM_SII902X is not set
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# CONFIG_DRM_SII9234 is not set
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# CONFIG_DRM_SIL_SII8620 is not set
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# CONFIG_DRM_SIMPLE_BRIDGE is not set
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# CONFIG_DRM_STI is not set
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# CONFIG_DRM_STM is not set
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# CONFIG_DRM_THINE_THC63LVD1024 is not set
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||||
# CONFIG_DRM_TIDSS is not set
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# CONFIG_DRM_TILCDC is not set
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# CONFIG_DRM_TI_SN65DSI86 is not set
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# CONFIG_DRM_TI_TFP410 is not set
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# CONFIG_DRM_TI_TPD12S015 is not set
|
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# CONFIG_DRM_TOSHIBA_TC358762 is not set
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# CONFIG_DRM_TOSHIBA_TC358764 is not set
|
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# CONFIG_DRM_TOSHIBA_TC358767 is not set
|
||||
# CONFIG_DRM_TOSHIBA_TC358768 is not set
|
||||
# CONFIG_DRM_TOSHIBA_TC358775 is not set
|
||||
# CONFIG_DRM_TVE200 is not set
|
||||
# CONFIG_DRM_VGEM is not set
|
||||
# CONFIG_DRM_VKMS is not set
|
||||
# CONFIG_FB_ARMCLCD is not set
|
||||
CONFIG_FB_CFB_COPYAREA=y
|
||||
CONFIG_FB_CFB_FILLRECT=y
|
||||
CONFIG_FB_CFB_IMAGEBLIT=y
|
||||
CONFIG_FB_CMDLINE=y
|
||||
CONFIG_FB_DEFERRED_IO=y
|
||||
# CONFIG_FB_FOREIGN_ENDIAN is not set
|
||||
# CONFIG_FB_IBM_GXT4500 is not set
|
||||
# CONFIG_FB_METRONOME is not set
|
||||
# CONFIG_FB_MODE_HELPERS is not set
|
||||
CONFIG_FB_NOTIFY=y
|
||||
# CONFIG_FB_OPENCORES is not set
|
||||
# CONFIG_FB_S1D13XXX is not set
|
||||
# CONFIG_FB_SIMPLE is not set
|
||||
# CONFIG_FB_SSD1307 is not set
|
||||
CONFIG_FB_SYS_COPYAREA=y
|
||||
CONFIG_FB_SYS_FILLRECT=y
|
||||
CONFIG_FB_SYS_FOPS=y
|
||||
CONFIG_FB_SYS_IMAGEBLIT=y
|
||||
# CONFIG_FB_TFT is not set
|
||||
# CONFIG_FB_TILEBLITTING is not set
|
||||
# CONFIG_FB_VIRTUAL is not set
|
||||
# CONFIG_FIRMWARE_EDID is not set
|
||||
CONFIG_HDMI=y
|
||||
CONFIG_I2C_ALGOBIT=y
|
||||
# CONFIG_LOGO is not set
|
||||
# CONFIG_LT7911D_FB_NOTIFIER is not set
|
||||
CONFIG_MEMORY_ISOLATION=y
|
||||
CONFIG_MFD_CORE=y
|
||||
CONFIG_MIGRATION=y
|
||||
CONFIG_REGMAP_IRQ=y
|
||||
# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set
|
||||
# CONFIG_RK_CMA_PROCFS is not set
|
||||
# CONFIG_RK_DMABUF_PROCFS is not set
|
||||
# CONFIG_ROCKCHIP_ANALOGIX_DP is not set
|
||||
# CONFIG_ROCKCHIP_CDN_DP is not set
|
||||
# CONFIG_ROCKCHIP_DRM_DEBUG is not set
|
||||
# CONFIG_ROCKCHIP_DRM_DIRECT_SHOW is not set
|
||||
# CONFIG_ROCKCHIP_DRM_TVE is not set
|
||||
# CONFIG_ROCKCHIP_DW_DP is not set
|
||||
# CONFIG_ROCKCHIP_DW_HDCP2 is not set
|
||||
# CONFIG_ROCKCHIP_DW_HDMI is not set
|
||||
# CONFIG_ROCKCHIP_DW_MIPI_DSI is not set
|
||||
# CONFIG_ROCKCHIP_INNO_HDMI is not set
|
||||
# CONFIG_ROCKCHIP_LVDS is not set
|
||||
CONFIG_ROCKCHIP_RGB=y
|
||||
# CONFIG_ROCKCHIP_RK3066_HDMI is not set
|
||||
# CONFIG_ROCKCHIP_RKNPU is not set
|
||||
# CONFIG_ROCKCHIP_VCONN is not set
|
||||
CONFIG_ROCKCHIP_VOP=y
|
||||
# CONFIG_ROCKCHIP_VOP2 is not set
|
||||
# CONFIG_SW_SYNC is not set
|
||||
# CONFIG_TINYDRM_HX8357D is not set
|
||||
# CONFIG_TINYDRM_ILI9225 is not set
|
||||
# CONFIG_TINYDRM_ILI9341 is not set
|
||||
# CONFIG_TINYDRM_ILI9486 is not set
|
||||
# CONFIG_TINYDRM_MI0283QT is not set
|
||||
# CONFIG_TINYDRM_REPAPER is not set
|
||||
# CONFIG_TINYDRM_ST7586 is not set
|
||||
# CONFIG_TINYDRM_ST7735R is not set
|
||||
# CONFIG_TOUCHSCREEN_AD7877 is not set
|
||||
# CONFIG_TOUCHSCREEN_AD7879 is not set
|
||||
# CONFIG_TOUCHSCREEN_ADC is not set
|
||||
# CONFIG_TOUCHSCREEN_ADS7846 is not set
|
||||
# CONFIG_TOUCHSCREEN_AR1021_I2C is not set
|
||||
# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
|
||||
# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
|
||||
# CONFIG_TOUCHSCREEN_BU21013 is not set
|
||||
# CONFIG_TOUCHSCREEN_BU21029 is not set
|
||||
# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set
|
||||
# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set
|
||||
# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
|
||||
# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set
|
||||
# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
|
||||
# CONFIG_TOUCHSCREEN_DYNAPRO is not set
|
||||
# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set
|
||||
# CONFIG_TOUCHSCREEN_EETI is not set
|
||||
# CONFIG_TOUCHSCREEN_EGALAX is not set
|
||||
# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set
|
||||
# CONFIG_TOUCHSCREEN_EKTF2127 is not set
|
||||
# CONFIG_TOUCHSCREEN_ELAN is not set
|
||||
# CONFIG_TOUCHSCREEN_ELAN5515 is not set
|
||||
# CONFIG_TOUCHSCREEN_ELO is not set
|
||||
# CONFIG_TOUCHSCREEN_EXC3000 is not set
|
||||
# CONFIG_TOUCHSCREEN_FTS is not set
|
||||
# CONFIG_TOUCHSCREEN_FUJITSU is not set
|
||||
# CONFIG_TOUCHSCREEN_GOODIX is not set
|
||||
# CONFIG_TOUCHSCREEN_GSL3673 is not set
|
||||
# CONFIG_TOUCHSCREEN_GSL3673_800X1280 is not set
|
||||
# CONFIG_TOUCHSCREEN_GSLX680_PAD is not set
|
||||
CONFIG_TOUCHSCREEN_GT1X=y
|
||||
# CONFIG_TOUCHSCREEN_GUNZE is not set
|
||||
# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
|
||||
# CONFIG_TOUCHSCREEN_HIDEEP is not set
|
||||
# CONFIG_TOUCHSCREEN_ILI210X is not set
|
||||
# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set
|
||||
# CONFIG_TOUCHSCREEN_INEXIO is not set
|
||||
# CONFIG_TOUCHSCREEN_IQS5XX is not set
|
||||
# CONFIG_TOUCHSCREEN_MAX11801 is not set
|
||||
# CONFIG_TOUCHSCREEN_MCS5000 is not set
|
||||
# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set
|
||||
# CONFIG_TOUCHSCREEN_MK712 is not set
|
||||
# CONFIG_TOUCHSCREEN_MMS114 is not set
|
||||
# CONFIG_TOUCHSCREEN_MTOUCH is not set
|
||||
# CONFIG_TOUCHSCREEN_PENMOUNT is not set
|
||||
# CONFIG_TOUCHSCREEN_PIXCIR is not set
|
||||
CONFIG_TOUCHSCREEN_PROPERTIES=y
|
||||
# CONFIG_TOUCHSCREEN_RM_TS is not set
|
||||
# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set
|
||||
# CONFIG_TOUCHSCREEN_S6SY761 is not set
|
||||
# CONFIG_TOUCHSCREEN_SILEAD is not set
|
||||
# CONFIG_TOUCHSCREEN_SIS_I2C is not set
|
||||
# CONFIG_TOUCHSCREEN_ST1232 is not set
|
||||
# CONFIG_TOUCHSCREEN_STMFTS is not set
|
||||
# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set
|
||||
# CONFIG_TOUCHSCREEN_SX8654 is not set
|
||||
# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
|
||||
# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
|
||||
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
|
||||
# CONFIG_TOUCHSCREEN_TPS6507X is not set
|
||||
# CONFIG_TOUCHSCREEN_TSC2004 is not set
|
||||
# CONFIG_TOUCHSCREEN_TSC2005 is not set
|
||||
# CONFIG_TOUCHSCREEN_TSC2007 is not set
|
||||
# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
|
||||
# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
|
||||
# CONFIG_TOUCHSCREEN_WACOM_I2C is not set
|
||||
# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
|
||||
# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set
|
||||
# CONFIG_TOUCHSCREEN_ZET6223 is not set
|
||||
# CONFIG_TOUCHSCREEN_ZFORCE is not set
|
||||
# CONFIG_TOUCHSCREEN_ZINITIX is not set
|
||||
# CONFIG_UDMABUF is not set
|
||||
CONFIG_VIDEOMODE_HELPERS=y
|
||||
# CONFIG_VIRTIO_DMA_SHARED_BUFFER is not set
|
||||
127
arch/arm/configs/rv1106-wakeup.config
Normal file
127
arch/arm/configs/rv1106-wakeup.config
Normal file
@@ -0,0 +1,127 @@
|
||||
CONFIG_INPUT=y
|
||||
CONFIG_RV1106_HPMCU_FAST_WAKEUP=y
|
||||
CONFIG_VIDEO_SC301IOT=y
|
||||
# CONFIG_VIDEO_SC3336 is not set
|
||||
CONFIG_VIDEO_SC3338=y
|
||||
# CONFIG_VIDEO_SC4336 is not set
|
||||
# CONFIG_VIDEO_SC530AI is not set
|
||||
CONFIG_HID=y
|
||||
# CONFIG_HIDRAW is not set
|
||||
# CONFIG_HID_A4TECH is not set
|
||||
# CONFIG_HID_ACRUX is not set
|
||||
# CONFIG_HID_ALPS is not set
|
||||
# CONFIG_HID_APPLE is not set
|
||||
# CONFIG_HID_AUREAL is not set
|
||||
# CONFIG_HID_BATTERY_STRENGTH is not set
|
||||
# CONFIG_HID_BELKIN is not set
|
||||
# CONFIG_HID_CHERRY is not set
|
||||
# CONFIG_HID_CMEDIA is not set
|
||||
# CONFIG_HID_COUGAR is not set
|
||||
# CONFIG_HID_CYPRESS is not set
|
||||
# CONFIG_HID_DRAGONRISE is not set
|
||||
# CONFIG_HID_ELECOM is not set
|
||||
# CONFIG_HID_EMS_FF is not set
|
||||
# CONFIG_HID_EZKEY is not set
|
||||
# CONFIG_HID_GEMBIRD is not set
|
||||
CONFIG_HID_GENERIC=y
|
||||
# CONFIG_HID_GFRM is not set
|
||||
# CONFIG_HID_GLORIOUS is not set
|
||||
# CONFIG_HID_GREENASIA is not set
|
||||
# CONFIG_HID_GYRATION is not set
|
||||
# CONFIG_HID_ICADE is not set
|
||||
# CONFIG_HID_ITE is not set
|
||||
# CONFIG_HID_JABRA is not set
|
||||
# CONFIG_HID_KENSINGTON is not set
|
||||
# CONFIG_HID_KEYTOUCH is not set
|
||||
# CONFIG_HID_KYE is not set
|
||||
# CONFIG_HID_LCPOWER is not set
|
||||
# CONFIG_HID_LENOVO is not set
|
||||
# CONFIG_HID_MACALLY is not set
|
||||
# CONFIG_HID_MAGICMOUSE is not set
|
||||
# CONFIG_HID_MALTRON is not set
|
||||
# CONFIG_HID_MAYFLASH is not set
|
||||
# CONFIG_HID_MICROSOFT is not set
|
||||
# CONFIG_HID_MONTEREY is not set
|
||||
# CONFIG_HID_MULTITOUCH is not set
|
||||
# CONFIG_HID_NINTENDO is not set
|
||||
# CONFIG_HID_NTI is not set
|
||||
# CONFIG_HID_ORTEK is not set
|
||||
# CONFIG_HID_PANTHERLORD is not set
|
||||
# CONFIG_HID_PETALYNX is not set
|
||||
# CONFIG_HID_PICOLCD is not set
|
||||
# CONFIG_HID_PLANTRONICS is not set
|
||||
# CONFIG_HID_PLAYSTATION is not set
|
||||
# CONFIG_HID_PRIMAX is not set
|
||||
# CONFIG_HID_REDRAGON is not set
|
||||
# CONFIG_HID_RMI is not set
|
||||
# CONFIG_HID_SAITEK is not set
|
||||
# CONFIG_HID_SENSOR_HUB is not set
|
||||
# CONFIG_HID_SMARTJOYPLUS is not set
|
||||
# CONFIG_HID_SPEEDLINK is not set
|
||||
# CONFIG_HID_STEAM is not set
|
||||
# CONFIG_HID_STEELSERIES is not set
|
||||
# CONFIG_HID_SUNPLUS is not set
|
||||
# CONFIG_HID_THRUSTMASTER is not set
|
||||
# CONFIG_HID_TIVO is not set
|
||||
# CONFIG_HID_TOPSEED is not set
|
||||
# CONFIG_HID_TWINHAN is not set
|
||||
# CONFIG_HID_UDRAW_PS3 is not set
|
||||
# CONFIG_HID_VIEWSONIC is not set
|
||||
# CONFIG_HID_VIVALDI is not set
|
||||
# CONFIG_HID_WALTOP is not set
|
||||
# CONFIG_HID_XINMO is not set
|
||||
# CONFIG_HID_ZEROPLUS is not set
|
||||
# CONFIG_HID_ZYDACRON is not set
|
||||
# CONFIG_I2C_HID is not set
|
||||
# CONFIG_INPUT_EVBUG is not set
|
||||
# CONFIG_INPUT_EVDEV is not set
|
||||
# CONFIG_INPUT_FF_MEMLESS is not set
|
||||
# CONFIG_INPUT_JOYDEV is not set
|
||||
# CONFIG_INPUT_JOYSTICK is not set
|
||||
CONFIG_INPUT_KEYBOARD=y
|
||||
# CONFIG_INPUT_MATRIXKMAP is not set
|
||||
# CONFIG_INPUT_MISC is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_INPUT_POLLDEV is not set
|
||||
# CONFIG_INPUT_SPARSEKMAP is not set
|
||||
# CONFIG_INPUT_TABLET is not set
|
||||
# CONFIG_INPUT_TOUCHSCREEN is not set
|
||||
# CONFIG_KEYBOARD_ADC is not set
|
||||
# CONFIG_KEYBOARD_ADP5588 is not set
|
||||
# CONFIG_KEYBOARD_ADP5589 is not set
|
||||
# CONFIG_KEYBOARD_ATKBD is not set
|
||||
# CONFIG_KEYBOARD_BCM is not set
|
||||
# CONFIG_KEYBOARD_CAP11XX is not set
|
||||
# CONFIG_KEYBOARD_DLINK_DIR685 is not set
|
||||
CONFIG_KEYBOARD_GPIO=y
|
||||
# CONFIG_KEYBOARD_GPIO_POLLED is not set
|
||||
# CONFIG_KEYBOARD_LKKBD is not set
|
||||
# CONFIG_KEYBOARD_LM8333 is not set
|
||||
# CONFIG_KEYBOARD_MATRIX is not set
|
||||
# CONFIG_KEYBOARD_MAX7359 is not set
|
||||
# CONFIG_KEYBOARD_MCS is not set
|
||||
# CONFIG_KEYBOARD_MPR121 is not set
|
||||
# CONFIG_KEYBOARD_NEWTON is not set
|
||||
# CONFIG_KEYBOARD_OMAP4 is not set
|
||||
# CONFIG_KEYBOARD_OPENCORES is not set
|
||||
# CONFIG_KEYBOARD_QT1050 is not set
|
||||
# CONFIG_KEYBOARD_QT1070 is not set
|
||||
# CONFIG_KEYBOARD_QT2160 is not set
|
||||
# CONFIG_KEYBOARD_SAMSUNG is not set
|
||||
# CONFIG_KEYBOARD_STOWAWAY is not set
|
||||
# CONFIG_KEYBOARD_SUNKBD is not set
|
||||
# CONFIG_KEYBOARD_TCA6416 is not set
|
||||
# CONFIG_KEYBOARD_TCA8418 is not set
|
||||
# CONFIG_KEYBOARD_XTKBD is not set
|
||||
# CONFIG_RC_CORE is not set
|
||||
# CONFIG_RMI4_CORE is not set
|
||||
# CONFIG_ROCKCHIP_REMOTECTL is not set
|
||||
# CONFIG_SENSORS_LIS3_I2C is not set
|
||||
# CONFIG_SENSORS_LIS3_SPI is not set
|
||||
# CONFIG_SENSOR_DEVICE is not set
|
||||
CONFIG_SND_JACK_INPUT_DEV=y
|
||||
# CONFIG_SND_SOC_CS42L52 is not set
|
||||
# CONFIG_SND_SOC_CS42L56 is not set
|
||||
# CONFIG_SND_SOC_WM8962 is not set
|
||||
# CONFIG_UHID is not set
|
||||
@@ -22,3 +22,9 @@ config ARCH_ROCKCHIP
|
||||
help
|
||||
Support for Rockchip's Cortex-A9 Single-to-Quad-Core-SoCs
|
||||
containing the RK2928, RK30xx and RK31xx series.
|
||||
|
||||
config RV1106_HPMCU_FAST_WAKEUP
|
||||
bool "Rockchip RV1106 HPMCU fast wakeup configuration support"
|
||||
depends on PM_SLEEP && CPU_RV1106
|
||||
help
|
||||
This config aims to support HPMCU fast wakeup.
|
||||
|
||||
@@ -15,6 +15,7 @@
|
||||
#include <asm/fiq_glue.h>
|
||||
#include <asm/tlbflush.h>
|
||||
#include <asm/suspend.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
|
||||
#include "rkpm_gicv2.h"
|
||||
#include "rkpm_helpers.h"
|
||||
@@ -91,6 +92,7 @@ static void __iomem *firewall_syssram_base;
|
||||
static void __iomem *pmu_base;
|
||||
static void __iomem *nstimer_base;
|
||||
static void __iomem *stimer_base;
|
||||
static void __iomem *mbox_base;
|
||||
static void __iomem *ddrc_base;
|
||||
static void __iomem *ioc_base[5];
|
||||
static void __iomem *gpio_base[5];
|
||||
@@ -309,7 +311,10 @@ static void gic400_save(void)
|
||||
|
||||
static void gic400_restore(void)
|
||||
{
|
||||
rkpm_gicv2_dist_restore(gicd_base, &gicd_ctx_save);
|
||||
if (IS_ENABLED(CONFIG_RV1106_HPMCU_FAST_WAKEUP))
|
||||
writel_relaxed(0x3, gicd_base + GIC_DIST_CTRL);
|
||||
else
|
||||
rkpm_gicv2_dist_restore(gicd_base, &gicd_ctx_save);
|
||||
rkpm_gicv2_cpu_restore(gicd_base, gicc_base, &gicc_ctx_save);
|
||||
}
|
||||
|
||||
@@ -410,6 +415,87 @@ static void __init rv1106_config_bootdata(void)
|
||||
rkpm_bootdata_l2ctlr = rv1106_l2_config();
|
||||
}
|
||||
|
||||
static void writel_clrset_bits(u32 clr, u32 set, void __iomem *addr)
|
||||
{
|
||||
u32 val = readl_relaxed(addr);
|
||||
|
||||
val &= ~clr;
|
||||
val |= set;
|
||||
writel_relaxed(val, addr);
|
||||
}
|
||||
|
||||
static void gic_irq_en(int irq)
|
||||
{
|
||||
writel_clrset_bits(0xff << irq % 4 * 8, 0x1 << irq % 4 * 8,
|
||||
gicd_base + GIC_DIST_TARGET + (irq >> 2 << 2));
|
||||
writel_clrset_bits(0xff << irq % 4 * 8, 0xa0 << irq % 4 * 8,
|
||||
gicd_base + GIC_DIST_PRI + (irq >> 2 << 2));
|
||||
writel_clrset_bits(0x3 << irq % 16 * 2, 0x1 << irq % 16 * 2,
|
||||
gicd_base + GIC_DIST_CONFIG + (irq >> 4 << 2));
|
||||
writel_clrset_bits(BIT(irq % 32), BIT(irq % 32),
|
||||
gicd_base + GIC_DIST_IGROUP + (irq >> 5 << 2));
|
||||
|
||||
dsb(sy);
|
||||
writel_relaxed(0x1 << irq % 32, gicd_base + GIC_DIST_ENABLE_SET + (irq >> 5 << 2));
|
||||
dsb(sy);
|
||||
}
|
||||
|
||||
static int is_hpmcu_mbox_int(void)
|
||||
{
|
||||
return !!(readl(mbox_base + RV1106_MBOX_B2A_STATUS) & BIT(0));
|
||||
}
|
||||
|
||||
static void hpmcu_start(void)
|
||||
{
|
||||
/* enable hpmcu mailbox AP irq */
|
||||
gic_irq_en(RV1106_HPMCU_MBOX_IRQ_AP);
|
||||
|
||||
/* tell hpmcu that we are currently in system wake up. */
|
||||
writel(RV1106_SYS_IS_WKUP, pmu_base + RV1106_PMU_SYS_REG(0));
|
||||
|
||||
/* set the mcu uncache area, usually set the devices address */
|
||||
writel(0xff000, coregrf_base + RV1106_COREGRF_CACHE_PERI_ADDR_START);
|
||||
writel(0xffc00, coregrf_base + RV1106_COREGRF_CACHE_PERI_ADDR_END);
|
||||
/* Reset the hp mcu */
|
||||
writel(0x1e001e, corecru_base + RV1106_COERCRU_SFTRST_CON(1));
|
||||
/* set the mcu addr */
|
||||
writel(RV1106_HPMCU_BOOT_ADDR,
|
||||
coresgrf_base + RV1106_CORESGRF_HPMCU_BOOTADDR);
|
||||
dsb(sy);
|
||||
|
||||
/* release the mcu */
|
||||
writel(0x1e0000, corecru_base + RV1106_COERCRU_SFTRST_CON(1));
|
||||
dsb(sy);
|
||||
}
|
||||
|
||||
static int hpmcu_fast_wkup(void)
|
||||
{
|
||||
u32 cmd;
|
||||
|
||||
hpmcu_start();
|
||||
|
||||
while (1) {
|
||||
rkpm_printstr("-s-\n");
|
||||
dsb(sy);
|
||||
wfi();
|
||||
rkpm_printstr("-w-\n");
|
||||
|
||||
if (is_hpmcu_mbox_int()) {
|
||||
rkpm_printstr("-h-mbox-\n");
|
||||
/* clear system wake up state */
|
||||
writel(0, pmu_base + RV1106_PMU_SYS_REG(0));
|
||||
writel(BIT(0), mbox_base + RV1106_MBOX_B2A_STATUS);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
cmd = readl(mbox_base + RV1106_MBOX_B2A_CMD_0);
|
||||
if (cmd == RV1106_MBOX_CMD_AP_SUSPEND)
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void clock_suspend(void)
|
||||
{
|
||||
int i;
|
||||
@@ -616,10 +702,11 @@ static void pmu_sleep_config(void)
|
||||
ddr_data.ioc1_1a_iomux_l = readl_relaxed(ioc_base[1] + 0);
|
||||
|
||||
pmu_wkup_con =
|
||||
/* BIT(RV1106_PMU_WAKEUP_TIMEROUT_EN) | */
|
||||
/* BIT(RV1106_PMU_WAKEUP_CPU_INT_EN) | */
|
||||
BIT(RV1106_PMU_WAKEUP_GPIO_INT_EN) |
|
||||
0;
|
||||
if (IS_ENABLED(CONFIG_RV1106_HPMCU_FAST_WAKEUP))
|
||||
pmu_wkup_con |= BIT(RV1106_PMU_WAKEUP_TIMEROUT_EN);
|
||||
|
||||
pmu_pwr_con =
|
||||
BIT(RV1106_PMU_PWRMODE_EN) |
|
||||
@@ -964,6 +1051,7 @@ static int rv1106_suspend_enter(suspend_state_t state)
|
||||
|
||||
rkpm_printch('-');
|
||||
|
||||
RE_ENTER_SLEEP:
|
||||
clock_suspend();
|
||||
rkpm_printch('0');
|
||||
|
||||
@@ -1001,6 +1089,17 @@ static int rv1106_suspend_enter(suspend_state_t state)
|
||||
clock_resume();
|
||||
rkpm_printch('-');
|
||||
|
||||
/* Check whether it's time_out wakeup */
|
||||
if (IS_ENABLED(CONFIG_RV1106_HPMCU_FAST_WAKEUP) && ddr_data.pmu_wkup_int_st == 0) {
|
||||
if (hpmcu_fast_wkup()) {
|
||||
rkpm_gicv2_dist_restore(gicd_base, &gicd_ctx_save);
|
||||
goto RE_ENTER_SLEEP;
|
||||
} else {
|
||||
rkpm_gicv2_dist_restore(gicd_base, &gicd_ctx_save);
|
||||
rkpm_gicv2_cpu_restore(gicd_base, gicc_base, &gicc_ctx_save);
|
||||
}
|
||||
}
|
||||
|
||||
fiq_glue_resume();
|
||||
|
||||
rv1106_dbg_irq_finish();
|
||||
@@ -1062,6 +1161,7 @@ static int __init rv1106_suspend_init(struct device_node *np)
|
||||
corecru_base = dev_reg_base + RV1106_CORECRU_OFFSET;
|
||||
venccru_base = dev_reg_base + RV1106_VENCCRU_OFFSET;
|
||||
vocru_base = dev_reg_base + RV1106_VOCRU_OFFSET;
|
||||
mbox_base = dev_reg_base + RV1106_MBOX_OFFSET;
|
||||
|
||||
ioc_base[0] = dev_reg_base + RV1106_GPIO0IOC_OFFSET;
|
||||
ioc_base[1] = dev_reg_base + RV1106_GPIO1IOC_OFFSET;
|
||||
|
||||
@@ -7,6 +7,7 @@
|
||||
#define __MACH_ROCKCHIP_RV1106_PM_H
|
||||
|
||||
#define RV1106_WAKEUP_TO_SYSTEM_RESET 0
|
||||
#define RV1106_HPMCU_FAST_WKUP_TIMEOUT 2000 /* ms */
|
||||
|
||||
#define RV1106_PERIGRF_OFFSET 0x0
|
||||
#define RV1106_VENCGRF_OFFSET 0x10000
|
||||
@@ -54,6 +55,7 @@
|
||||
|
||||
#define RV1106_NSTIMER_OFFSET 0x580000
|
||||
#define RV1106_STIMER_OFFSET 0x590000
|
||||
#define RV1106_MBOX_OFFSET 0x5c0000
|
||||
#define RV1106_PMUSRAM_OFFSET 0x670000
|
||||
#define RV1106_DDRC_OFFSET 0x800000
|
||||
#define RV1106_FW_DDR_OFFSET 0x900000
|
||||
@@ -101,6 +103,7 @@
|
||||
#define RV1106_CORECRU_GATE_CON(i) (0x800 + (i) * 4)
|
||||
#define RV1106_COERCRU_CLKSEL_CON(i) (0x300 + (i) * 4)
|
||||
#define RV1106_CORECRU_GATE_CON_NUM 2
|
||||
#define RV1106_COERCRU_SFTRST_CON(i) (0xa00 + (i) * 4)
|
||||
|
||||
/* grf */
|
||||
#define RV1106_PMUGRF_SOC_CON(i) ((i) * 4)
|
||||
@@ -110,6 +113,11 @@
|
||||
|
||||
#define RV1106_DDRGRF_CON(i) ((i) * 0x4)
|
||||
|
||||
#define RV1106_CORESGRF_HPMCU_BOOTADDR 0x44
|
||||
|
||||
#define RV1106_COREGRF_CACHE_PERI_ADDR_START 0x24
|
||||
#define RV1106_COREGRF_CACHE_PERI_ADDR_END 0x28
|
||||
|
||||
/* pvmt */
|
||||
#define RV1106_PVTM_CON(i) (0x4 + (i) * 4)
|
||||
#define RV1106_PVTM_INTEN 0x70
|
||||
@@ -177,6 +185,17 @@
|
||||
#define PMU_SUSPEND_MAGIC 0x02468ace
|
||||
#define PMU_RESUME_MAGIC 0x13579bdf
|
||||
|
||||
/* mcu */
|
||||
#define RV1106_MBOX_B2A_STATUS 0x2c
|
||||
#define RV1106_MBOX_B2A_CMD_0 0x30
|
||||
|
||||
#define RV1106_HPMCU_MBOX_IRQ_AP 33
|
||||
|
||||
#define RV1106_HPMCU_BOOT_ADDR 0x40000
|
||||
#define RV1106_MBOX_CMD_AP_SUSPEND 0x12345600
|
||||
#define RV1106_MBOX_CMD_AP_RESUME 0x12345601
|
||||
#define RV1106_SYS_IS_WKUP 0x87654300
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
extern unsigned long rkpm_bootdata_cpusp;
|
||||
extern unsigned long rkpm_bootdata_cpu_code;
|
||||
|
||||
@@ -20,6 +20,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308bs-evb-ddr3-v20-rk618-rgb2dsi.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308bs-evb-dmic-pdm-v11.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308bs-evb-mcu-display-v20.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308bs-evb-mipi-display-v11.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308bs-evb-rgb-display-v20.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-lp3-v10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-lp3-v10-avb.dtb
|
||||
|
||||
139
arch/arm64/boot/dts/rockchip/rk3308bs-evb-rgb-display-v20.dts
Normal file
139
arch/arm64/boot/dts/rockchip/rk3308bs-evb-rgb-display-v20.dts
Normal file
@@ -0,0 +1,139 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3308bs-evb-amic-v11.dts"
|
||||
|
||||
/ {
|
||||
model = "Rockchip RK3308B-S EVB DDR3 V20 Board + Rockchip RK3308 RGB ExtBoard V10";
|
||||
compatible = "rockchip,rk3308bs-evb-rgb-display-v20", "rockchip,rk3308";
|
||||
|
||||
backlight: backlight {
|
||||
status = "okay";
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm1 0 25000 0>;
|
||||
brightness-levels = <
|
||||
0 1 2 3 4 5 6 7
|
||||
8 9 10 11 12 13 14 15
|
||||
16 17 18 19 20 21 22 23
|
||||
24 25 26 27 28 29 30 31
|
||||
32 33 34 35 36 37 38 39
|
||||
40 41 42 43 44 45 46 47
|
||||
48 49 50 51 52 53 54 55
|
||||
56 57 58 59 60 61 62 63
|
||||
64 65 66 67 68 69 70 71
|
||||
72 73 74 75 76 77 78 79
|
||||
80 81 82 83 84 85 86 87
|
||||
88 89 90 91 92 93 94 95
|
||||
96 97 98 99 100 101 102 103
|
||||
104 105 106 107 108 109 110 111
|
||||
112 113 114 115 116 117 118 119
|
||||
120 121 122 123 124 125 126 127
|
||||
128 129 130 131 132 133 134 135
|
||||
136 137 138 139 140 141 142 143
|
||||
144 145 146 147 148 149 150 151
|
||||
152 153 154 155 156 157 158 159
|
||||
160 161 162 163 164 165 166 167
|
||||
168 169 170 171 172 173 174 175
|
||||
176 177 178 179 180 181 182 183
|
||||
184 185 186 187 188 189 190 191
|
||||
192 193 194 195 196 197 198 199
|
||||
200 201 202 203 204 205 206 207
|
||||
208 209 210 211 212 213 214 215
|
||||
216 217 218 219 220 221 222 223
|
||||
224 225 226 227 228 229 230 231
|
||||
232 233 234 235 236 237 238 239
|
||||
240 241 242 243 244 245 246 247
|
||||
248 249 250 251 252 253 254 255>;
|
||||
default-brightness-level = <200>;
|
||||
};
|
||||
|
||||
panel: panel {
|
||||
compatible = "simple-panel";
|
||||
bus-format = <MEDIA_BUS_FMT_RGB888_1X24>;
|
||||
backlight = <&backlight>;
|
||||
enable-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
enable-delay-ms = <20>;
|
||||
reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
|
||||
reset-value = <0>;
|
||||
reset-delay-ms = <10>;
|
||||
status = "okay";
|
||||
|
||||
display-timings {
|
||||
native-mode = <&fx070_dhm11boe_timing>;
|
||||
|
||||
fx070_dhm11boe_timing: timing0 {
|
||||
clock-frequency = <50000000>;
|
||||
hactive = <1024>;
|
||||
vactive = <600>;
|
||||
hback-porch = <140>;
|
||||
hfront-porch = <160>;
|
||||
vback-porch = <20>;
|
||||
vfront-porch = <20>;
|
||||
hsync-len = <20>;
|
||||
vsync-len = <2>; //value range <2~22>
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <0>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
port {
|
||||
panel_in_rgb: endpoint {
|
||||
remote-endpoint = <&rgb_out_panel>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
cma {
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
size = <0x0 0x800000>;
|
||||
linux,cma-default;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&display_subsystem {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rgb {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lcdc_ctl &lcdc_rgb888_m1>;
|
||||
|
||||
ports {
|
||||
rgb_out: port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rgb_out_panel: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&panel_in_rgb>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&route_rgb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1030,24 +1030,24 @@
|
||||
spi0_pins: spi0-pins {
|
||||
rockchip,pins =
|
||||
/* spi0_clk */
|
||||
<4 RK_PB4 2 &pcfg_pull_none>,
|
||||
<4 RK_PB4 2 &pcfg_pull_none_drv_level_2>,
|
||||
/* spi0_miso */
|
||||
<4 RK_PB3 2 &pcfg_pull_none>,
|
||||
<4 RK_PB3 2 &pcfg_pull_none_drv_level_2>,
|
||||
/* spi0_mosi */
|
||||
<4 RK_PB2 2 &pcfg_pull_none>;
|
||||
<4 RK_PB2 2 &pcfg_pull_none_drv_level_2>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
spi0_csn0: spi0-csn0 {
|
||||
rockchip,pins =
|
||||
/* spi0_csn0 */
|
||||
<4 RK_PB6 2 &pcfg_pull_none>;
|
||||
<4 RK_PB6 2 &pcfg_pull_none_drv_level_2>;
|
||||
};
|
||||
/omit-if-no-ref/
|
||||
spi0_csn1: spi0-csn1 {
|
||||
rockchip,pins =
|
||||
/* spi0_csn1 */
|
||||
<4 RK_PC1 2 &pcfg_pull_none>;
|
||||
<4 RK_PC1 2 &pcfg_pull_none_drv_level_2>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -1056,24 +1056,24 @@
|
||||
spi1_pins: spi1-pins {
|
||||
rockchip,pins =
|
||||
/* spi1_clk */
|
||||
<1 RK_PB6 2 &pcfg_pull_none>,
|
||||
<1 RK_PB6 2 &pcfg_pull_none_drv_level_2>,
|
||||
/* spi1_miso */
|
||||
<1 RK_PC0 2 &pcfg_pull_none>,
|
||||
<1 RK_PC0 2 &pcfg_pull_none_drv_level_2>,
|
||||
/* spi1_mosi */
|
||||
<1 RK_PB7 2 &pcfg_pull_none>;
|
||||
<1 RK_PB7 2 &pcfg_pull_none_drv_level_2>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
spi1_csn0: spi1-csn0 {
|
||||
rockchip,pins =
|
||||
/* spi1_csn0 */
|
||||
<1 RK_PC1 1 &pcfg_pull_none>;
|
||||
<1 RK_PC1 1 &pcfg_pull_none_drv_level_2>;
|
||||
};
|
||||
/omit-if-no-ref/
|
||||
spi1_csn1: spi1-csn1 {
|
||||
rockchip,pins =
|
||||
/* spi1_csn1 */
|
||||
<1 RK_PC2 1 &pcfg_pull_none>;
|
||||
<1 RK_PC2 1 &pcfg_pull_none_drv_level_2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -928,6 +928,7 @@
|
||||
};
|
||||
|
||||
&u2phy0_otg {
|
||||
rockchip,sel-pipe-phystatus;
|
||||
vbus-supply = <&vbus5v0_typec>;
|
||||
};
|
||||
|
||||
|
||||
@@ -332,6 +332,64 @@ rockchip_rk3066_pll_clk_set_by_auto(struct rockchip_clk_pll *pll,
|
||||
return rate_table;
|
||||
}
|
||||
|
||||
static u32
|
||||
rockchip_rk3588_pll_frac_get(u32 m, u32 p, u32 s, u64 fin_hz, u64 fvco)
|
||||
{
|
||||
u64 fref, fout, ffrac;
|
||||
u32 k = 0;
|
||||
|
||||
fref = fin_hz / p;
|
||||
ffrac = fvco - (m * fref);
|
||||
fout = ffrac * 65536;
|
||||
k = fout / fref;
|
||||
if (k > 32767) {
|
||||
fref = fin_hz / p;
|
||||
ffrac = ((m + 1) * fref) - fvco;
|
||||
fout = ffrac * 65536;
|
||||
k = ((fout * 10 / fref) + 7) / 10;
|
||||
if (k > 32767)
|
||||
k = 0;
|
||||
else
|
||||
k = ~k + 1;
|
||||
}
|
||||
return k;
|
||||
}
|
||||
|
||||
static struct rockchip_pll_rate_table *
|
||||
rockchip_rk3588_pll_frac_by_auto(unsigned long fin_hz, unsigned long fout_hz)
|
||||
{
|
||||
struct rockchip_pll_rate_table *rate_table = rk_pll_rate_table_get();
|
||||
u64 fvco_min = 2250 * MHZ, fvco_max = 4500 * MHZ;
|
||||
u32 p, m, s, k;
|
||||
u64 fvco;
|
||||
|
||||
for (s = 0; s <= 6; s++) {
|
||||
fvco = (u64)fout_hz << s;
|
||||
if (fvco < fvco_min || fvco > fvco_max)
|
||||
continue;
|
||||
for (p = 1; p <= 4; p++) {
|
||||
for (m = 64; m <= 1023; m++) {
|
||||
if ((fvco >= m * fin_hz / p) && (fvco < (m + 1) * fin_hz / p)) {
|
||||
k = rockchip_rk3588_pll_frac_get(m, p, s,
|
||||
(u64)fin_hz,
|
||||
fvco);
|
||||
if (!k)
|
||||
continue;
|
||||
rate_table->p = p;
|
||||
rate_table->s = s;
|
||||
rate_table->k = k;
|
||||
if (k > 32767)
|
||||
rate_table->m = m + 1;
|
||||
else
|
||||
rate_table->m = m;
|
||||
return rate_table;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static struct rockchip_pll_rate_table *
|
||||
rockchip_rk3588_pll_clk_set_by_auto(struct rockchip_clk_pll *pll,
|
||||
unsigned long fin_hz,
|
||||
@@ -341,7 +399,7 @@ rockchip_rk3588_pll_clk_set_by_auto(struct rockchip_clk_pll *pll,
|
||||
u64 fvco_min = 2250 * MHZ, fvco_max = 4500 * MHZ;
|
||||
u64 fout_min = 37 * MHZ, fout_max = 4500 * MHZ;
|
||||
u32 p, m, s;
|
||||
u64 fvco, fref, fout, ffrac;
|
||||
u64 fvco;
|
||||
|
||||
if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz)
|
||||
return NULL;
|
||||
@@ -368,26 +426,11 @@ rockchip_rk3588_pll_clk_set_by_auto(struct rockchip_clk_pll *pll,
|
||||
}
|
||||
pr_err("CANNOT FIND Fout by auto,fout = %lu\n", fout_hz);
|
||||
} else {
|
||||
for (s = 0; s <= 6; s++) {
|
||||
fvco = (u64)fout_hz << s;
|
||||
if (fvco < fvco_min || fvco > fvco_max)
|
||||
continue;
|
||||
for (p = 1; p <= 4; p++) {
|
||||
for (m = 64; m <= 1023; m++) {
|
||||
if ((fvco >= m * fin_hz / p) && (fvco < (m + 1) * fin_hz / p)) {
|
||||
rate_table->p = p;
|
||||
rate_table->m = m;
|
||||
rate_table->s = s;
|
||||
fref = fin_hz / p;
|
||||
ffrac = fvco - (m * fref);
|
||||
fout = ffrac * 65536;
|
||||
rate_table->k = fout / fref;
|
||||
return rate_table;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
pr_err("CANNOT FIND Fout by auto,fout = %lu\n", fout_hz);
|
||||
rate_table = rockchip_rk3588_pll_frac_by_auto(fin_hz, fout_hz);
|
||||
if (!rate_table)
|
||||
pr_err("CANNOT FIND Fout by auto,fout = %lu\n", fout_hz);
|
||||
else
|
||||
return rate_table;
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
@@ -1345,7 +1388,17 @@ static unsigned long rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw,
|
||||
rate64 *= cur.m;
|
||||
do_div(rate64, cur.p);
|
||||
|
||||
if (cur.k) {
|
||||
if (cur.k & BIT(15)) {
|
||||
/* fractional mode */
|
||||
u64 frac_rate64;
|
||||
|
||||
cur.k = (~(cur.k - 1)) & RK3588_PLLCON2_K_MASK;
|
||||
frac_rate64 = prate * cur.k;
|
||||
postdiv = cur.p;
|
||||
postdiv *= 65536;
|
||||
do_div(frac_rate64, postdiv);
|
||||
rate64 -= frac_rate64;
|
||||
} else {
|
||||
/* fractional mode */
|
||||
u64 frac_rate64 = prate * cur.k;
|
||||
|
||||
@@ -1516,7 +1569,7 @@ int rockchip_pll_clk_compensation(struct clk *clk, int ppm)
|
||||
{
|
||||
struct clk *parent = clk_get_parent(clk);
|
||||
struct rockchip_clk_pll *pll;
|
||||
static u32 frac, fbdiv;
|
||||
static u32 frac, fbdiv, s, p;
|
||||
bool negative;
|
||||
u32 pllcon, pllcon0, pllcon2, fbdiv_mask, frac_mask, frac_shift;
|
||||
u64 fracdiv, m, n;
|
||||
@@ -1567,11 +1620,6 @@ int rockchip_pll_clk_compensation(struct clk *clk, int ppm)
|
||||
negative = !!(ppm & BIT(31));
|
||||
ppm = negative ? ~ppm + 1 : ppm;
|
||||
|
||||
if (!frac) {
|
||||
frac = readl_relaxed(pll->reg_base + pllcon2) & frac_mask;
|
||||
fbdiv = readl_relaxed(pll->reg_base + pllcon0) & fbdiv_mask;
|
||||
}
|
||||
|
||||
switch (pll->type) {
|
||||
case pll_rk3036:
|
||||
case pll_rk3328:
|
||||
@@ -1583,6 +1631,10 @@ int rockchip_pll_clk_compensation(struct clk *clk, int ppm)
|
||||
* 1 << 24 1 << 24 1000000
|
||||
*
|
||||
*/
|
||||
if (!frac) {
|
||||
frac = readl_relaxed(pll->reg_base + pllcon2) & frac_mask;
|
||||
fbdiv = readl_relaxed(pll->reg_base + pllcon0) & fbdiv_mask;
|
||||
}
|
||||
m = div64_u64((uint64_t)frac * ppm, 1000000);
|
||||
n = div64_u64((uint64_t)ppm << 24, 1000000) * fbdiv;
|
||||
|
||||
@@ -1597,13 +1649,65 @@ int rockchip_pll_clk_compensation(struct clk *clk, int ppm)
|
||||
writel_relaxed(pllcon, pll->reg_base + pllcon2);
|
||||
break;
|
||||
case pll_rk3588:
|
||||
m = div64_u64((uint64_t)frac * ppm, 100000);
|
||||
n = div64_u64((uint64_t)ppm * 65535 * fbdiv, 100000);
|
||||
if (!fbdiv) {
|
||||
frac = readl_relaxed(pll->reg_base + pllcon2) & frac_mask;
|
||||
fbdiv = readl_relaxed(pll->reg_base + pllcon0) & fbdiv_mask;
|
||||
}
|
||||
if (!frac) {
|
||||
pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(1));
|
||||
s = ((pllcon >> RK3588_PLLCON1_S_SHIFT)
|
||||
& RK3588_PLLCON1_S_MASK);
|
||||
p = ((pllcon >> RK3588_PLLCON1_P_SHIFT)
|
||||
& RK3588_PLLCON1_P_MASK);
|
||||
m = div64_u64((uint64_t)clk_get_rate(clk) * ppm, 24000000);
|
||||
n = div64_u64((uint64_t)m * 65536 * p * (1 << s), 1000000);
|
||||
|
||||
fracdiv = negative ? frac - (div64_u64(m + n, 10)) : frac + (div64_u64(m + n, 10));
|
||||
|
||||
if (!frac || fracdiv > frac_mask)
|
||||
return -EINVAL;
|
||||
if (n > 32767)
|
||||
return -EINVAL;
|
||||
fracdiv = negative ? ~n + 1 : n;
|
||||
} else if (frac & BIT(15)) {
|
||||
frac = (~(frac - 1)) & RK3588_PLLCON2_K_MASK;
|
||||
m = div64_u64((uint64_t)frac * ppm, 100000);
|
||||
n = div64_u64((uint64_t)ppm * 65536 * fbdiv, 100000);
|
||||
if (negative) {
|
||||
fracdiv = frac + (div64_u64(m + n, 10));
|
||||
if (fracdiv > 32767)
|
||||
return -EINVAL;
|
||||
fracdiv = ~fracdiv + 1;
|
||||
} else {
|
||||
s = div64_u64(m + n, 10);
|
||||
if (frac >= s) {
|
||||
fracdiv = frac - s;
|
||||
if (fracdiv > 32767)
|
||||
return -EINVAL;
|
||||
fracdiv = ~fracdiv + 1;
|
||||
} else {
|
||||
fracdiv = s - frac;
|
||||
if (fracdiv > 32767)
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
m = div64_u64((uint64_t)frac * ppm, 100000);
|
||||
n = div64_u64((uint64_t)ppm * 65536 * fbdiv, 100000);
|
||||
if (!negative) {
|
||||
fracdiv = frac + (div64_u64(m + n, 10));
|
||||
if (fracdiv > 32767)
|
||||
return -EINVAL;
|
||||
} else {
|
||||
s = div64_u64(m + n, 10);
|
||||
if (frac >= s) {
|
||||
fracdiv = frac - s;
|
||||
if (fracdiv > 32767)
|
||||
return -EINVAL;
|
||||
} else {
|
||||
fracdiv = s - frac;
|
||||
if (fracdiv > 32767)
|
||||
return -EINVAL;
|
||||
fracdiv = ~fracdiv + 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
writel_relaxed(HIWORD_UPDATE(fracdiv, frac_mask, frac_shift),
|
||||
pll->reg_base + pllcon2);
|
||||
|
||||
@@ -79,16 +79,16 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = {
|
||||
RK3588_PLL_RATE(1008000000, 2, 336, 2, 0),
|
||||
RK3588_PLL_RATE(1000000000, 3, 500, 2, 0),
|
||||
RK3588_PLL_RATE(983040000, 4, 655, 2, 23592),
|
||||
RK3588_PLL_RATE(955520000, 3, 477, 2, 49806),
|
||||
RK3588_PLL_RATE(955520000, 3, 478, 2, 49807),
|
||||
RK3588_PLL_RATE(903168000, 6, 903, 2, 11009),
|
||||
RK3588_PLL_RATE(900000000, 2, 300, 2, 0),
|
||||
RK3588_PLL_RATE(816000000, 2, 272, 2, 0),
|
||||
RK3588_PLL_RATE(786432000, 2, 262, 2, 9437),
|
||||
RK3588_PLL_RATE(786000000, 1, 131, 2, 0),
|
||||
RK3588_PLL_RATE(785560000, 3, 392, 2, 51117),
|
||||
RK3588_PLL_RATE(785560000, 3, 393, 2, 51119),
|
||||
RK3588_PLL_RATE(722534400, 8, 963, 2, 24850),
|
||||
RK3588_PLL_RATE(600000000, 2, 200, 2, 0),
|
||||
RK3588_PLL_RATE(594000000, 2, 198, 2, 0),
|
||||
RK3588_PLL_RATE(594000000, 1, 99, 2, 0),
|
||||
RK3588_PLL_RATE(408000000, 2, 272, 3, 0),
|
||||
RK3588_PLL_RATE(312000000, 2, 208, 3, 0),
|
||||
RK3588_PLL_RATE(216000000, 2, 288, 4, 0),
|
||||
|
||||
@@ -51,6 +51,7 @@
|
||||
#define SC530AI_LINK_FREQ_396M 198000000 // 396Mbps
|
||||
#define SC530AI_LINK_FREQ_792M 396000000 // 792Mbps
|
||||
#define SC530AI_LINK_FREQ_792M_2LANE 396000000 // 792Mbps
|
||||
#define SC530AI_LINK_FREQ_936M_2LANE 468000000 // 936Mbps
|
||||
|
||||
#define SC530AI_LINEAR_PIXEL_RATES (SC530AI_LINK_FREQ_396M / 10 * 2 * 4)
|
||||
#define SC530AI_HDR_PIXEL_RATES (SC530AI_LINK_FREQ_792M / 10 * 2 * 4)
|
||||
@@ -519,18 +520,22 @@ static const struct regval sc530ai_10_30fps_2880x1620_2lane_regs[] = {
|
||||
{0x37f9, 0x80},
|
||||
{0x3018, 0x32},
|
||||
{0x3019, 0x0c},
|
||||
{0x301f, 0x18},
|
||||
{0x301f, 0x42},
|
||||
{0x320c, 0x06},
|
||||
{0x320d, 0x27},
|
||||
{0x320e, 0x07},
|
||||
{0x320f, 0xbc},
|
||||
{0x3250, 0x40},
|
||||
{0x3251, 0x98},
|
||||
{0x3253, 0x0c},
|
||||
{0x325f, 0x20},
|
||||
{0x3301, 0x08},
|
||||
{0x3304, 0x50},
|
||||
{0x3306, 0x78},
|
||||
{0x3306, 0x88},
|
||||
{0x3308, 0x14},
|
||||
{0x3309, 0x70},
|
||||
{0x330a, 0x00},
|
||||
{0x330b, 0xd8},
|
||||
{0x330b, 0xf8},
|
||||
{0x330d, 0x10},
|
||||
{0x331e, 0x41},
|
||||
{0x331f, 0x61},
|
||||
@@ -559,18 +564,18 @@ static const struct regval sc530ai_10_30fps_2880x1620_2lane_regs[] = {
|
||||
{0x33ae, 0x30},
|
||||
{0x33af, 0x50},
|
||||
{0x33b1, 0x80},
|
||||
{0x33b2, 0x80},
|
||||
{0x33b3, 0x40},
|
||||
{0x33b2, 0x48},
|
||||
{0x33b3, 0x30},
|
||||
{0x349f, 0x02},
|
||||
{0x34a6, 0x48},
|
||||
{0x34a7, 0x49},
|
||||
{0x34a8, 0x40},
|
||||
{0x34a9, 0x30},
|
||||
{0x34f8, 0x4b},
|
||||
{0x34f9, 0x30},
|
||||
{0x34a7, 0x4b},
|
||||
{0x34a8, 0x30},
|
||||
{0x34a9, 0x18},
|
||||
{0x34f8, 0x5f},
|
||||
{0x34f9, 0x08},
|
||||
{0x3632, 0x48},
|
||||
{0x3633, 0x32},
|
||||
{0x3637, 0x2b},
|
||||
{0x3637, 0x29},
|
||||
{0x3638, 0xc1},
|
||||
{0x363b, 0x20},
|
||||
{0x363d, 0x02},
|
||||
@@ -581,7 +586,7 @@ static const struct regval sc530ai_10_30fps_2880x1620_2lane_regs[] = {
|
||||
{0x367c, 0x40},
|
||||
{0x367d, 0x48},
|
||||
{0x3690, 0x32},
|
||||
{0x3691, 0x32},
|
||||
{0x3691, 0x43},
|
||||
{0x3692, 0x33},
|
||||
{0x3693, 0x40},
|
||||
{0x3694, 0x4b},
|
||||
@@ -593,7 +598,10 @@ static const struct regval sc530ai_10_30fps_2880x1620_2lane_regs[] = {
|
||||
{0x36a3, 0x4b},
|
||||
{0x36a4, 0x4f},
|
||||
{0x36d0, 0x01},
|
||||
{0x36ea, 0x0d},
|
||||
{0x36eb, 0x04},
|
||||
{0x36ec, 0x03},
|
||||
{0x36ed, 0x14},
|
||||
{0x370f, 0x01},
|
||||
{0x3722, 0x00},
|
||||
{0x3728, 0x10},
|
||||
@@ -602,8 +610,10 @@ static const struct regval sc530ai_10_30fps_2880x1620_2lane_regs[] = {
|
||||
{0x37b2, 0x83},
|
||||
{0x37b3, 0x48},
|
||||
{0x37b4, 0x49},
|
||||
{0x37fb, 0x25},
|
||||
{0x37fa, 0x0d},
|
||||
{0x37fb, 0x24},
|
||||
{0x37fc, 0x01},
|
||||
{0x37fd, 0x14},
|
||||
{0x3901, 0x00},
|
||||
{0x3902, 0xc5},
|
||||
{0x3904, 0x08},
|
||||
@@ -613,19 +623,20 @@ static const struct regval sc530ai_10_30fps_2880x1620_2lane_regs[] = {
|
||||
{0x391f, 0x44},
|
||||
{0x3926, 0x21},
|
||||
{0x3929, 0x18},
|
||||
{0x3933, 0x81},
|
||||
{0x3934, 0x81},
|
||||
{0x3937, 0x69},
|
||||
{0x3933, 0x82},
|
||||
{0x3934, 0x0a},
|
||||
{0x3937, 0x5f},
|
||||
{0x3939, 0x00},
|
||||
{0x393a, 0x00},
|
||||
{0x39dc, 0x02},
|
||||
{0x3e01, 0xcd},
|
||||
{0x3e02, 0xa0},
|
||||
{0x3e01, 0xf6},
|
||||
{0x3e02, 0xe0},
|
||||
{0x440e, 0x02},
|
||||
{0x4509, 0x20},
|
||||
{0x4800, 0x04},
|
||||
{0x4837, 0x14},
|
||||
{0x4837, 0x22},
|
||||
{0x5010, 0x10},
|
||||
{0x5780, 0x66},
|
||||
{0x578d, 0x40},
|
||||
{0x5799, 0x06},
|
||||
{0x57ad, 0x00},
|
||||
{0x5ae0, 0xfe},
|
||||
@@ -657,8 +668,7 @@ static const struct regval sc530ai_10_30fps_2880x1620_2lane_regs[] = {
|
||||
{0x5afe, 0x30},
|
||||
{0x5aff, 0x28},
|
||||
{0x36e9, 0x44},
|
||||
{0x37f9, 0x34},
|
||||
// {0x0100, 0x01},
|
||||
{0x37f9, 0x44},
|
||||
{REG_NULL, 0x00},
|
||||
};
|
||||
|
||||
@@ -712,10 +722,10 @@ static const struct sc530ai_mode supported_modes_2lane[] = {
|
||||
},
|
||||
.exp_def = 0xcda / 2,
|
||||
.hts_def = 0xb40,
|
||||
.vts_def = 0x0672,
|
||||
.vts_def = 0x07bc,
|
||||
.bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
|
||||
.reg_list = sc530ai_10_30fps_2880x1620_2lane_regs,
|
||||
.mipi_freq_idx = 2,
|
||||
.mipi_freq_idx = 3,
|
||||
.bpp = 10,
|
||||
.hdr_mode = NO_HDR,
|
||||
.vc[PAD0] = 0,
|
||||
@@ -726,6 +736,7 @@ static const s64 link_freq_items[] = {
|
||||
SC530AI_LINK_FREQ_396M,
|
||||
SC530AI_LINK_FREQ_792M,
|
||||
SC530AI_LINK_FREQ_792M_2LANE,
|
||||
SC530AI_LINK_FREQ_936M_2LANE,
|
||||
};
|
||||
|
||||
/* Write registers up to 4 at a time */
|
||||
|
||||
@@ -5302,6 +5302,7 @@ static void rkcif_sync_crop_info(struct rkcif_stream *stream)
|
||||
stream->crop_mask |= CROP_SRC_SENSOR_MASK;
|
||||
dev->terminal_sensor.selection = input_sel;
|
||||
} else {
|
||||
stream->crop_mask &= ~CROP_SRC_SENSOR_MASK;
|
||||
dev->terminal_sensor.selection.r = dev->terminal_sensor.raw_rect;
|
||||
}
|
||||
}
|
||||
@@ -5322,8 +5323,10 @@ static void rkcif_sync_crop_info(struct rkcif_stream *stream)
|
||||
stream->crop[CROP_SRC_ACT].top = stream->crop[CROP_SRC_USR].top +
|
||||
stream->crop[CROP_SRC_SENSOR].top;
|
||||
}
|
||||
} else {
|
||||
} else if (stream->crop_mask & CROP_SRC_SENSOR_MASK) {
|
||||
stream->crop[CROP_SRC_ACT] = stream->crop[CROP_SRC_SENSOR];
|
||||
} else {
|
||||
stream->crop[CROP_SRC_ACT] = dev->terminal_sensor.raw_rect;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -1209,6 +1209,13 @@ static int spinand_init_flash(struct spinand_device *spinand)
|
||||
if (ret)
|
||||
break;
|
||||
|
||||
/* HWP_EN must be enabled first before block unlock region is set */
|
||||
if (spinand->id.data[0] == 0x01) {
|
||||
ret = spinand_lock_block(spinand, HWP_EN);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = spinand_lock_block(spinand, BL_ALL_UNLOCKED);
|
||||
if (ret)
|
||||
break;
|
||||
|
||||
@@ -213,6 +213,15 @@ static const struct spinand_info dosilicon_spinand_table[] = {
|
||||
SPINAND_HAS_QE_BIT,
|
||||
SPINAND_ECCINFO(&ds35xxgb_ooblayout,
|
||||
ds35xxgb_ecc_get_status)),
|
||||
SPINAND_INFO("DS35Q1GD-IB",
|
||||
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51),
|
||||
NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
|
||||
NAND_ECCREQ(8, 512),
|
||||
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
|
||||
&write_cache_variants,
|
||||
&update_cache_variants),
|
||||
SPINAND_HAS_QE_BIT,
|
||||
SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)),
|
||||
};
|
||||
|
||||
static const struct spinand_manufacturer_ops dosilicon_spinand_manuf_ops = {
|
||||
|
||||
@@ -29,7 +29,7 @@ static SPINAND_OP_VARIANTS(update_cache_variants,
|
||||
SPINAND_PROG_LOAD(false, 0, NULL, 0));
|
||||
|
||||
static int f50lxx41x_ooblayout_ecc(struct mtd_info *mtd, int section,
|
||||
struct mtd_oob_region *region)
|
||||
struct mtd_oob_region *region)
|
||||
{
|
||||
if (section > 3)
|
||||
return -ERANGE;
|
||||
@@ -41,7 +41,7 @@ static int f50lxx41x_ooblayout_ecc(struct mtd_info *mtd, int section,
|
||||
}
|
||||
|
||||
static int f50lxx41x_ooblayout_free(struct mtd_info *mtd, int section,
|
||||
struct mtd_oob_region *region)
|
||||
struct mtd_oob_region *region)
|
||||
{
|
||||
if (section > 3)
|
||||
return -ERANGE;
|
||||
@@ -57,6 +57,60 @@ static const struct mtd_ooblayout_ops f50lxx41x_ooblayout = {
|
||||
.free = f50lxx41x_ooblayout_free,
|
||||
};
|
||||
|
||||
static int f50l2g41ka_ooblayout_ecc(struct mtd_info *mtd, int section,
|
||||
struct mtd_oob_region *region)
|
||||
{
|
||||
if (section)
|
||||
return -ERANGE;
|
||||
|
||||
region->offset = mtd->oobsize / 2;
|
||||
region->length = mtd->oobsize / 2;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int f50l2g41ka_ooblayout_free(struct mtd_info *mtd, int section,
|
||||
struct mtd_oob_region *region)
|
||||
{
|
||||
if (section)
|
||||
return -ERANGE;
|
||||
|
||||
region->offset = 2;
|
||||
region->length = mtd->oobsize / 2 - 2;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct mtd_ooblayout_ops f50l2g41ka_ooblayout = {
|
||||
.ecc = f50l2g41ka_ooblayout_ecc,
|
||||
.free = f50l2g41ka_ooblayout_free,
|
||||
};
|
||||
|
||||
/*
|
||||
* ecc bits: 0xC0[4,6]
|
||||
* [0b000], No bit errors were detected;
|
||||
* [0b001] and [0b011], 1~6 Bit errors were detected and corrected. Not
|
||||
* reach Flipping Bits;
|
||||
* [0b101], Bit error count equals the bit flip
|
||||
* detection threshold
|
||||
* [0b010], Multiple bit errors were detected and
|
||||
* not corrected.
|
||||
* others, Reserved.
|
||||
*/
|
||||
static int f50l2g41ka_ecc_ecc_get_status(struct spinand_device *spinand,
|
||||
u8 status)
|
||||
{
|
||||
struct nand_device *nand = spinand_to_nand(spinand);
|
||||
u8 eccsr = (status & GENMASK(6, 4)) >> 4;
|
||||
|
||||
if (eccsr <= 1 || eccsr == 3)
|
||||
return eccsr;
|
||||
else if (eccsr == 5)
|
||||
return nanddev_get_ecc_requirements(nand)->strength;
|
||||
else
|
||||
return -EBADMSG;
|
||||
}
|
||||
|
||||
static const struct spinand_info esmt_spinand_table[] = {
|
||||
SPINAND_INFO("F50L1G41LB",
|
||||
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x01),
|
||||
@@ -67,6 +121,15 @@ static const struct spinand_info esmt_spinand_table[] = {
|
||||
&update_cache_variants),
|
||||
0,
|
||||
SPINAND_ECCINFO(&f50lxx41x_ooblayout, NULL)),
|
||||
SPINAND_INFO("F50L2G41KA",
|
||||
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x41, 0x7F),
|
||||
NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
|
||||
NAND_ECCREQ(8, 512),
|
||||
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
|
||||
&write_cache_variants,
|
||||
&update_cache_variants),
|
||||
0,
|
||||
SPINAND_ECCINFO(&f50l2g41ka_ooblayout, f50l2g41ka_ecc_ecc_get_status)),
|
||||
};
|
||||
|
||||
static const struct spinand_manufacturer_ops esmt_spinand_manuf_ops = {
|
||||
|
||||
@@ -416,7 +416,7 @@ static const struct spinand_info gigadevice_spinand_table[] = {
|
||||
SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
|
||||
gd5fxgq5xexxg_ecc_get_status)),
|
||||
SPINAND_INFO("GD5F1GQ5RExxG",
|
||||
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x41),
|
||||
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x41, 0xc8),
|
||||
NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
|
||||
NAND_ECCREQ(4, 512),
|
||||
SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
|
||||
|
||||
@@ -332,6 +332,33 @@ static const struct spinand_info xtx_spinand_table[] = {
|
||||
SPINAND_HAS_QE_BIT,
|
||||
SPINAND_ECCINFO(&xt26g01c_ooblayout,
|
||||
xt26g11c_ecc_get_status)),
|
||||
SPINAND_INFO("XT26Q02DWSIGA",
|
||||
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x52),
|
||||
NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
|
||||
NAND_ECCREQ(8, 512),
|
||||
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
|
||||
&write_cache_variants,
|
||||
&update_cache_variants),
|
||||
SPINAND_HAS_QE_BIT,
|
||||
SPINAND_ECCINFO(&xt26g01c_ooblayout, xt26g11c_ecc_get_status)),
|
||||
SPINAND_INFO("XT26Q01DWSIGA",
|
||||
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51),
|
||||
NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
|
||||
NAND_ECCREQ(8, 512),
|
||||
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
|
||||
&write_cache_variants,
|
||||
&update_cache_variants),
|
||||
SPINAND_HAS_QE_BIT,
|
||||
SPINAND_ECCINFO(&xt26g01c_ooblayout, xt26g11c_ecc_get_status)),
|
||||
SPINAND_INFO("XT26Q04DWSIGA",
|
||||
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x53),
|
||||
NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
|
||||
NAND_ECCREQ(8, 512),
|
||||
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
|
||||
&write_cache_variants,
|
||||
&update_cache_variants),
|
||||
SPINAND_HAS_QE_BIT,
|
||||
SPINAND_ECCINFO(&xt26g01c_ooblayout, xt26g11c_ecc_get_status)),
|
||||
};
|
||||
|
||||
static const struct spinand_manufacturer_ops xtx_spinand_manuf_ops = {
|
||||
|
||||
@@ -973,6 +973,7 @@ static void rkvdec2_link_try_dequeue(struct mpp_dev *mpp)
|
||||
|
||||
list_move_tail(&task->table->link, &link_dec->unused_list);
|
||||
list_del_init(&mpp_task->queue_link);
|
||||
link_dec->task_running--;
|
||||
|
||||
set_bit(TASK_STATE_HANDLE, &mpp_task->state);
|
||||
set_bit(TASK_STATE_PROC_DONE, &mpp_task->state);
|
||||
@@ -981,13 +982,10 @@ static void rkvdec2_link_try_dequeue(struct mpp_dev *mpp)
|
||||
if (test_bit(TASK_STATE_ABORT, &mpp_task->state))
|
||||
set_bit(TASK_STATE_ABORT_READY, &mpp_task->state);
|
||||
|
||||
wake_up(&mpp_task->wait);
|
||||
kref_put(&mpp_task->ref, rkvdec2_link_free_task);
|
||||
link_dec->task_running--;
|
||||
|
||||
mpp_dbg_link("session %d task %d irq_status %#08x timeout %d abort %d\n",
|
||||
mpp_task->session->index, mpp_task->task_index,
|
||||
irq_status, timeout_flag, abort_flag);
|
||||
|
||||
if (irq_status & RKVDEC_INT_ERROR_MASK) {
|
||||
dev_err(mpp->dev,
|
||||
"session %d task %d irq_status %#08x timeout %u abort %u\n",
|
||||
@@ -996,6 +994,9 @@ static void rkvdec2_link_try_dequeue(struct mpp_dev *mpp)
|
||||
if (!reset_flag)
|
||||
atomic_inc(&mpp->reset_request);
|
||||
}
|
||||
|
||||
wake_up(&mpp_task->wait);
|
||||
kref_put(&mpp_task->ref, rkvdec2_link_free_task);
|
||||
}
|
||||
|
||||
/* resend running task after reset */
|
||||
|
||||
@@ -149,6 +149,7 @@
|
||||
/* feature register */
|
||||
#define REG_BLOCK_LOCK 0xa0
|
||||
#define BL_ALL_UNLOCKED 0x00
|
||||
#define HWP_EN 0x02 /* Skyhigh feature, Hardware write protection */
|
||||
|
||||
/* configuration register */
|
||||
#define REG_CFG 0xb0
|
||||
|
||||
@@ -977,6 +977,20 @@ static int rockchip_i2s_probe(struct platform_device *pdev)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = rockchip_i2s_init_dai(i2s, res, &dai);
|
||||
if (ret)
|
||||
goto err_clk;
|
||||
|
||||
/*
|
||||
* MUST: after pm_runtime_enable step, any register R/W
|
||||
* should be wrapped with pm_runtime_get_sync/put.
|
||||
*
|
||||
* Another approach is to enable the regcache true to
|
||||
* avoid access HW registers.
|
||||
*
|
||||
* Alternatively, performing the registers R/W before
|
||||
* pm_runtime_enable is also a good option.
|
||||
*/
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
if (!pm_runtime_enabled(&pdev->dev)) {
|
||||
ret = i2s_runtime_resume(&pdev->dev);
|
||||
@@ -984,10 +998,6 @@ static int rockchip_i2s_probe(struct platform_device *pdev)
|
||||
goto err_pm_disable;
|
||||
}
|
||||
|
||||
ret = rockchip_i2s_init_dai(i2s, res, &dai);
|
||||
if (ret)
|
||||
goto err_pm_disable;
|
||||
|
||||
ret = devm_snd_soc_register_component(&pdev->dev,
|
||||
&rockchip_i2s_component,
|
||||
dai, 1);
|
||||
@@ -1015,7 +1025,7 @@ err_suspend:
|
||||
i2s_runtime_suspend(&pdev->dev);
|
||||
err_pm_disable:
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
err_clk:
|
||||
clk_disable_unprepare(i2s->hclk);
|
||||
|
||||
return ret;
|
||||
|
||||
@@ -1004,6 +1004,23 @@ static int rockchip_pdm_probe(struct platform_device *pdev)
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
rockchip_pdm_set_samplerate(pdm, PDM_DEFAULT_RATE);
|
||||
rockchip_pdm_rxctrl(pdm, 0);
|
||||
|
||||
ret = rockchip_pdm_path_parse(pdm, node);
|
||||
if (ret != 0 && ret != -ENOENT)
|
||||
goto err_clk;
|
||||
|
||||
/*
|
||||
* MUST: after pm_runtime_enable step, any register R/W
|
||||
* should be wrapped with pm_runtime_get_sync/put.
|
||||
*
|
||||
* Another approach is to enable the regcache true to
|
||||
* avoid access HW registers.
|
||||
*
|
||||
* Alternatively, performing the registers R/W before
|
||||
* pm_runtime_enable is also a good option.
|
||||
*/
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
if (!pm_runtime_enabled(&pdev->dev)) {
|
||||
ret = rockchip_pdm_runtime_resume(&pdev->dev);
|
||||
@@ -1020,13 +1037,6 @@ static int rockchip_pdm_probe(struct platform_device *pdev)
|
||||
goto err_suspend;
|
||||
}
|
||||
|
||||
rockchip_pdm_set_samplerate(pdm, PDM_DEFAULT_RATE);
|
||||
rockchip_pdm_rxctrl(pdm, 0);
|
||||
|
||||
ret = rockchip_pdm_path_parse(pdm, node);
|
||||
if (ret != 0 && ret != -ENOENT)
|
||||
goto err_suspend;
|
||||
|
||||
if (of_property_read_bool(node, "rockchip,no-dmaengine")) {
|
||||
dev_info(&pdev->dev, "Used for Multi-DAI\n");
|
||||
return 0;
|
||||
@@ -1047,7 +1057,7 @@ err_suspend:
|
||||
rockchip_pdm_runtime_suspend(&pdev->dev);
|
||||
err_pm_disable:
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
err_clk:
|
||||
clk_disable_unprepare(pdm->hclk);
|
||||
|
||||
return ret;
|
||||
|
||||
Reference in New Issue
Block a user