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https://github.com/hardkernel/linux.git
synced 2026-06-10 21:07:02 +09:00
usb: support for rk3026
This commit is contained in:
lyz
@@ -147,3 +147,52 @@ static int __init bvalid_init(void)
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}
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late_initcall(bvalid_init);
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#endif
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#if defined(IRQ_OTG0_ID) && defined(CONFIG_ARCH_RK3026)
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#include <linux/io.h>
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#include <mach/iomux.h>
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static irqreturn_t otg_id_irq_handler(int irq, void *dev_id)
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{
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unsigned int uoc_con;
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/* clear irq */
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uoc_con = readl_relaxed(RK2928_GRF_BASE + GRF_UOC_CON);
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#ifdef CONFIG_RK_USB_UART
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/* to do @lyz*/
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#endif
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if(uoc_con & (1<<1)) //id rise
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{
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writel_relaxed((0x1 << 16) | 0x1, RK2928_GRF_BASE + GRF_UOC_CON);;//clear id rise irq pandding
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}
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if(uoc_con & (1<<3))//id fall
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{
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writel_relaxed((0x3 << 16) | 0x3, RK2928_GRF_BASE + GRF_UOC_CON);;//clear id fall irq pandding
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}
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rk28_send_wakeup_key();
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return IRQ_HANDLED;
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}
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static int __init otg_id_irq_init(void)
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{
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int ret;
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int irq = IRQ_OTG0_ID;
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ret = request_irq(irq, otg_id_irq_handler, 0, "otg_id_change", NULL);
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if (ret < 0) {
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pr_err("%s: request_irq(%d) failed\n", __func__, irq);
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return ret;
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}
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/* clear & enable otg change irq */
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/* for rk3026 enable and clear id_fall_irq & id_rise_irq*/
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writel_relaxed((0xf << 16) | 0xf, RK2928_GRF_BASE + GRF_UOC_CON);
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enable_irq_wake(irq);
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return 0;
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}
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late_initcall(otg_id_irq_init);
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#endif
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@@ -29,6 +29,6 @@ dwc_otg-objs := dwc_otg_driver.o dwc_otg_attr.o
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dwc_otg-objs += dwc_otg_cil.o dwc_otg_cil_intr.o
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dwc_otg-objs += dwc_otg_pcd.o dwc_otg_pcd_intr.o
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dwc_otg-objs += dwc_otg_hcd.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o
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dwc_otg-objs += usbdev_rk30.o usbdev_rk2928.o
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dwc_otg-objs += usbdev_rk30.o usbdev_rk2928.o usbdev_rk3026.o
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obj-$(CONFIG_DWC_OTG) := dwc_otg.o
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418
drivers/usb/dwc_otg/usbdev_rk3026.c
Executable file
418
drivers/usb/dwc_otg/usbdev_rk3026.c
Executable file
@@ -0,0 +1,418 @@
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/clk.h>
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#include <mach/irqs.h>
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#include <mach/gpio.h>
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#include <mach/iomux.h>
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#include <mach/cru.h>
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#ifdef CONFIG_RK_CONFIG
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#include <mach/config.h>
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#endif
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#include "usbdev_rk.h"
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#include "dwc_otg_regs.h"
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#ifdef CONFIG_ARCH_RK3026
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#define GRF_REG_BASE RK2928_GRF_BASE
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#define USBOTG_SIZE RK2928_USBOTG20_SIZE
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#define USBGRF_SOC_STATUS0 (GRF_REG_BASE+0x14c)
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#define USBGRF_UOC0_CON0 (GRF_REG_BASE+0x17c)
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#define USBGRF_UOC1_CON0 (GRF_REG_BASE+0X190)
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#define USBGRF_UOC1_CON1 (GRF_REG_BASE+0x194)
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int dwc_otg_check_dpdm(void)
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{
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static uint8_t * reg_base = 0;
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volatile unsigned int * otg_dctl;
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volatile unsigned int * otg_gotgctl;
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volatile unsigned int * otg_hprt0;
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int bus_status = 0;
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unsigned int * otg_phy_con0 = (unsigned int*)(USBGRF_UOC0_CON0) ;
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*(unsigned int*)(RK2928_CRU_BASE+0x120) = ((7<<5)<<16)|(7<<5); // otg0 phy clkgate
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udelay(3);
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*(unsigned int*)(RK2928_CRU_BASE+0x120) = ((7<<5)<<16)|(0<<5); // otg0 phy clkgate
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dsb();
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*(unsigned int*)(RK2928_CRU_BASE+0xd4) = ((1<<5)<<16); // otg0 phy clkgate
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*(unsigned int*)(RK2928_CRU_BASE+0xe4) = ((1<<13)<<16); // otg0 hclk clkgate
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*(unsigned int*)(RK2928_CRU_BASE+0xf4) = ((3<<10)<<16); // hclk usb clkgat
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// exit phy suspend
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*otg_phy_con0 = ((0x01<<0)<<16);
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// soft connect
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if(reg_base == 0){
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reg_base = ioremap(RK2928_USBOTG20_PHYS,USBOTG_SIZE);
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if(!reg_base){
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bus_status = -1;
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goto out;
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}
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}
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mdelay(105);
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//printk("regbase %p 0x%x, otg_phy_con%p, 0x%x\n",
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// reg_base, *(reg_base), otg_phy_con1, *otg_phy_con1);
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otg_dctl = (unsigned int * )(reg_base+0x804);
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otg_gotgctl = (unsigned int * )(reg_base);
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otg_hprt0 = (unsigned int * )(reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET);
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if(*otg_gotgctl &(1<<19)){
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bus_status = 1;
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//*(unsigned int*)(GRF_REG_BASE + GRF_UOC0_CON0) = 0x10000000;//exit usbphy io hi-z state ***NO NEED FOR
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*otg_dctl &= ~(0x01<<1);//exit soft-disconnect mode
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mdelay(1); // delay about 1ms
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// check dp,dm
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if((*otg_hprt0 & 0xc00)==0xc00)//check hprt[11:10]
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bus_status = 2;
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//*(unsigned int*)(GRF_REG_BASE + GRF_UOC0_CON0) = 0x10001000;
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}
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out:
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return bus_status;
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}
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EXPORT_SYMBOL(dwc_otg_check_dpdm);
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#ifdef CONFIG_USB20_OTG
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/*DWC_OTG*/
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static struct resource usb20_otg_resource[] = {
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{
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.start = IRQ_USB_OTG,
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.end = IRQ_USB_OTG,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = RK2928_USBOTG20_PHYS,
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.end = RK2928_USBOTG20_PHYS + RK2928_USBOTG20_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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void usb20otg_hw_init(void)
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{
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#ifndef CONFIG_USB20_HOST
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// close USB 2.0 HOST phy and clock
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unsigned int * otg_phy_con1 = (unsigned int*)(USBGRF_UOC1_CON1);
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*otg_phy_con1 = 0x1D5 |(0x1ff<<16); // enter suspend.
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#endif
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// usb phy config init
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// other hardware init
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#ifdef CONFIG_RK_CONFIG
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otg_drv_init(0);
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#else
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rk30_mux_api_set(GPIO3_C1, 1);
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#endif
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}
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void usb20otg_phy_suspend(void* pdata, int suspend)
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{
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struct dwc_otg_platform_data *usbpdata=pdata;
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unsigned int * otg_phy_con1 = (unsigned int*)(USBGRF_UOC0_CON0);
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if(suspend){
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*otg_phy_con1 = 0x55 |(0x7f<<16); // enter suspend.
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usbpdata->phy_status = 1;
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}
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else{
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*otg_phy_con1 = (0x01<<16); // exit suspend.
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usbpdata->phy_status = 0;
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}
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}
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void usb20otg_soft_reset(void)
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{
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#if 0 //@lyz todo for 3028 phy
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printk("~~~~~~~~~~usb20otg_soft_reset\n");
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//phy reset
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*(unsigned int*)(USBGRF_UOC0_CON0) = 0x00030001;
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*(unsigned int*)(USBGRF_UOC1_CON1) = 0x00030001;
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cru_set_soft_reset(SOFT_RST_USBPOR, true);
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cru_set_soft_reset(SOFT_RST_UTMI0, true);
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cru_set_soft_reset(SOFT_RST_UTMI1, true);
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udelay(15);
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*(unsigned int*)(USBGRF_UOC0_CON0) = 0x00030002;
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*(unsigned int*)(USBGRF_UOC1_CON1) = 0x00030002;
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udelay(1500);
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cru_set_soft_reset(SOFT_RST_USBPOR, false);
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udelay(2);
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cru_set_soft_reset(SOFT_RST_UTMI0, false);
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cru_set_soft_reset(SOFT_RST_UTMI1, false);
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//ctrler reset
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cru_set_soft_reset(SOFT_RST_OTGC0, true);
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cru_set_soft_reset(SOFT_RST_OTGC1, true);
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udelay(2);
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cru_set_soft_reset(SOFT_RST_USBOTG0, true);
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cru_set_soft_reset(SOFT_RST_USBOTG1, true);
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udelay(2);
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cru_set_soft_reset(SOFT_RST_OTGC0,false);
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cru_set_soft_reset(SOFT_RST_OTGC1,false);
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cru_set_soft_reset(SOFT_RST_USBOTG0,false);
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cru_set_soft_reset(SOFT_RST_USBOTG1,false);
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#endif
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}
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void usb20otg_clock_init(void* pdata)
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{
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struct dwc_otg_platform_data *usbpdata=pdata;
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struct clk* ahbclk,*phyclk;
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ahbclk = clk_get(NULL, "hclk_otg0");
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phyclk = clk_get(NULL, "otgphy0");
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usbpdata->phyclk = phyclk;
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usbpdata->ahbclk = ahbclk;
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}
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void usb20otg_clock_enable(void* pdata, int enable)
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{
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struct dwc_otg_platform_data *usbpdata=pdata;
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#if 1
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if(enable){
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clk_enable(usbpdata->ahbclk);
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clk_enable(usbpdata->phyclk);
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}
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else{
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// clk_disable(usbpdata->phyclk); /* otg/host20 use the same phyclk, so can't disable phyclk in case host20 is used.*/
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clk_disable(usbpdata->ahbclk);
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}
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#endif
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}
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int usb20otg_get_status(int id)
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{
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int ret = -1;
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unsigned int usbgrf_status = *(unsigned int*)(USBGRF_SOC_STATUS0);
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unsigned int uoc1_con0 = *(unsigned int*)(USBGRF_UOC1_CON0);
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switch(id)
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{
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case USB_STATUS_BVABLID:
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// bvalid in grf
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ret = (usbgrf_status &(1<<7));
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break;
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case USB_STATUS_DPDM:
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// dpdm in grf
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ret = (usbgrf_status &(3<<8));
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break;
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case USB_STATUS_ID:
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// id in grf
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ret = (usbgrf_status &(1<<10));
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break;
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case USB_STATUS_UARTMODE:
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// usb_uart_mode in grf
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ret = (uoc1_con0 &(1<<13));
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default:
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break;
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}
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return ret;
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}
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void dwc_otg_uart_mode(void* pdata, int enter_usb_uart_mode)
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{
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#ifdef CONFIG_RK_USB_UART
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//struct dwc_otg_platform_data *usbpdata=pdata;//1:uart 0:usb
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unsigned int * otg_phy_con0 = (unsigned int*)(USBGRF_UOC1_CON0);
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//printk("usb_uart_mode = %d,enter_usb_uart_mode = %d\n",otg_phy_con1,enter_usb_uart_mode);
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if(1 == enter_usb_uart_mode) //uart mode
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{
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*otg_phy_con0 = (0x03 << 12 | (0x03<<(16+12)));//bypass dm
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//printk("phy enter uart mode USBGRF_UOC1_CON0 = %08x\n",*otg_phy_con1);
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}
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if(0 == enter_usb_uart_mode) //usb mode
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{
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*otg_phy_con0 = (0x03<<(12+16)); //bypass dm disable
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//printk("phy enter usb mode USBGRF_UOC1_CON0 = %8x\n",*otg_phy_con1);
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}
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#endif
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}
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void usb20otg_power_enable(int enable)
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{
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#ifdef CONFIG_RK_CONFIG
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if(enable)
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otg_drv_on();
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else
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otg_drv_off();
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#endif
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}
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struct dwc_otg_platform_data usb20otg_pdata = {
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.phyclk = NULL,
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.ahbclk = NULL,
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.busclk = NULL,
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.phy_status = 0,
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.hw_init=usb20otg_hw_init,
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.phy_suspend=usb20otg_phy_suspend,
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.soft_reset=usb20otg_soft_reset,
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.clock_init=usb20otg_clock_init,
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.clock_enable=usb20otg_clock_enable,
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.get_status=usb20otg_get_status,
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.dwc_otg_uart_mode=dwc_otg_uart_mode,
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};
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struct platform_device device_usb20_otg = {
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.name = "usb20_otg",
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.id = -1,
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.num_resources = ARRAY_SIZE(usb20_otg_resource),
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.resource = usb20_otg_resource,
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.dev = {
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.platform_data = &usb20otg_pdata,
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},
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};
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#endif
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#ifdef CONFIG_USB20_HOST
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static struct resource usb20_host_resource[] = {
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{
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.start = IRQ_USB_HOST,
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.end = IRQ_USB_HOST,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = RK2928_USBHOST20_PHYS,
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.end = RK2928_USBHOST20_PHYS + RK2928_USBHOST20_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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void usb20host_hw_init(void)
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{
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// usb phy config init
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// other haredware init
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#ifdef CONFIG_RK_CONFIG
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host_drv_init(1);
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#endif
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}
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void usb20host_phy_suspend(void* pdata, int suspend)
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{
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struct dwc_otg_platform_data *usbpdata=pdata;
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unsigned int * otg_phy_con1 = (unsigned int*)(USBGRF_UOC1_CON1);
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if(suspend){
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//*otg_phy_con2 = (1 << 12 | 1 << (12+16));//host io set to High-Z state ***NO NEED FOR 3026
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*otg_phy_con1 = 0x1D5 |(0x1ff<<16); // enter suspend.
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usbpdata->phy_status = 1;
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}
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else{
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//*otg_phy_con2 = (1 << 12+16);//host io exit High-Z state ***NO NEED FOR 3026
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*otg_phy_con1 = (0x01<<16); // exit suspend.
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usbpdata->phy_status = 0;
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}
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}
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void usb20host_soft_reset(void)
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{
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#if 0
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cru_set_soft_reset(SOFT_RST_USBOTG1, true);
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//cru_set_soft_reset(SOFT_RST_USBPHY1, true);
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cru_set_soft_reset(SOFT_RST_OTGC1, true);
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udelay(1);
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cru_set_soft_reset(SOFT_RST_USBOTG1, false);
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//cru_set_soft_reset(SOFT_RST_USBPHY1, false);
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cru_set_soft_reset(SOFT_RST_OTGC1, false);
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mdelay(1);
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#endif
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}
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void usb20host_clock_init(void* pdata)
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{
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struct dwc_otg_platform_data *usbpdata=pdata;
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struct clk* ahbclk,*phyclk;
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ahbclk = clk_get(NULL, "hclk_otg1");
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phyclk = clk_get(NULL, "otgphy1");
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usbpdata->phyclk = phyclk;
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usbpdata->ahbclk = ahbclk;
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}
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void usb20host_clock_enable(void* pdata, int enable)
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{
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struct dwc_otg_platform_data *usbpdata=pdata;
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#if 1
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if(enable){
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clk_enable(usbpdata->ahbclk);
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clk_enable(usbpdata->phyclk);
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}
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else{
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clk_disable(usbpdata->phyclk);
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clk_disable(usbpdata->ahbclk);
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}
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#endif
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}
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int usb20host_get_status(int id)
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{
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int ret = -1;
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unsigned int usbgrf_status = *(unsigned int*)(USBGRF_SOC_STATUS0);
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switch(id)
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{
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case USB_STATUS_BVABLID:
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// bvalid in grf
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ret = (usbgrf_status &(1<<12));
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break;
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case USB_STATUS_DPDM:
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// dpdm in grf
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ret = (usbgrf_status &(3<<13));
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break;
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case USB_STATUS_ID:
|
||||
// id in grf
|
||||
ret = 0;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
void usb20host_power_enable(int enable)
|
||||
{
|
||||
#ifdef CONFIG_RK_CONFIG
|
||||
if(enable)
|
||||
host_drv_on();
|
||||
else
|
||||
host_drv_off();
|
||||
#endif
|
||||
}
|
||||
struct dwc_otg_platform_data usb20host_pdata = {
|
||||
.phyclk = NULL,
|
||||
.ahbclk = NULL,
|
||||
.busclk = NULL,
|
||||
.phy_status = 0,
|
||||
.hw_init=usb20host_hw_init,
|
||||
.phy_suspend=usb20host_phy_suspend,
|
||||
.soft_reset=usb20host_soft_reset,
|
||||
.clock_init=usb20host_clock_init,
|
||||
.clock_enable=usb20host_clock_enable,
|
||||
.get_status=usb20host_get_status,
|
||||
};
|
||||
|
||||
struct platform_device device_usb20_host = {
|
||||
.name = "usb20_host",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(usb20_host_resource),
|
||||
.resource = usb20_host_resource,
|
||||
.dev = {
|
||||
.platform_data = &usb20host_pdata,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
static int __init usbdev_init_devices(void)
|
||||
{
|
||||
int ret = 0;
|
||||
#ifdef CONFIG_USB20_OTG
|
||||
ret = platform_device_register(&device_usb20_otg);
|
||||
if(ret < 0){
|
||||
printk("%s: platform_device_register(usb20_otg) failed\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_USB20_HOST
|
||||
ret = platform_device_register(&device_usb20_host);
|
||||
#endif
|
||||
return ret;
|
||||
}
|
||||
arch_initcall(usbdev_init_devices);
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user