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arm64: dts: rockchip: change naneng combphy ref clock to 100mhz for rk3568

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When using 24MHz reference clock, some devices can't identify
the SATA PM chip, And the signal quality is not as good as 100MHz.
so change the reference clock to 100MHz.

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: If7d951a0b77d503f9faf1c1f88c78a9e07471e47
This commit is contained in:
Yifeng Zhao
2021-05-21 16:09:00 +08:00
committed by Tao Huang
parent 3d0af15013
commit 8a38d9f53b
1 changed files with 2 additions and 2 deletions
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4
arch/arm64/boot/dts/rockchip/rk3568.dtsi
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@@ -3086,7 +3086,7 @@
<&cru PCLK_PIPE>;
clock-names = "refclk", "apbclk", "pipe_clk";
assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
assigned-clock-rates = <24000000>;
assigned-clock-rates = <100000000>;
resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>;
reset-names = "combphy-apb", "combphy";
rockchip,pipe-grf = <&pipegrf>;
@@ -3102,7 +3102,7 @@
<&cru PCLK_PIPE>;
clock-names = "refclk", "apbclk", "pipe_clk";
assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
assigned-clock-rates = <24000000>;
assigned-clock-rates = <100000000>;
resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>;
reset-names = "combphy-apb", "combphy";
rockchip,pipe-grf = <&pipegrf>;