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ANDROID: KVM: arm64: Split up nvhe/fixed_config.h
In preparation for using some of the pKVM fixed configuration register definitions to filter the available VM CAPs in the host, split the nvhe/fixed_config.h header so that the definitions can be shared with the host, while keeping the hypervisor function prototypes in the nvhe/ namespace. Signed-off-by: Will Deacon <will@kernel.org> Signed-off-by: Will Deacon <willdeacon@google.com> Bug: 233587962 Change-Id: I33894868e7652f7b79caa91a007dccad997ef4ab
This commit is contained in:
Will Deacon
@@ -2,12 +2,14 @@
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/*
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* Copyright (C) 2020 - Google LLC
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* Author: Quentin Perret <qperret@google.com>
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* Author: Fuad Tabba <tabba@google.com>
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*/
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#ifndef __ARM64_KVM_PKVM_H__
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#define __ARM64_KVM_PKVM_H__
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#include <linux/memblock.h>
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#include <asm/kvm_pgtable.h>
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#include <asm/sysreg.h>
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/* Maximum number of VMs that can co-exist under pKVM. */
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#define KVM_MAX_PVMS 255
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@@ -18,6 +20,194 @@ int pkvm_init_host_vm(struct kvm *kvm);
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int pkvm_create_hyp_vm(struct kvm *kvm);
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void pkvm_destroy_hyp_vm(struct kvm *kvm);
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/*
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* Definitions for features to be allowed or restricted for guest virtual
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* machines, depending on the mode KVM is running in and on the type of guest
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* that is running.
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*
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* The ALLOW masks represent a bitmask of feature fields that are allowed
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* without any restrictions as long as they are supported by the system.
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*
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* The RESTRICT_UNSIGNED masks, if present, represent unsigned fields for
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* features that are restricted to support at most the specified feature.
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*
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* If a feature field is not present in either, than it is not supported.
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*
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* The approach taken for protected VMs is to allow features that are:
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* - Needed by common Linux distributions (e.g., floating point)
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* - Trivial to support, e.g., supporting the feature does not introduce or
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* require tracking of additional state in KVM
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* - Cannot be trapped or prevent the guest from using anyway
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*/
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/*
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* Allow for protected VMs:
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* - Floating-point and Advanced SIMD
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* - Data Independent Timing
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*/
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#define PVM_ID_AA64PFR0_ALLOW (\
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ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_FP) | \
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ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AdvSIMD) | \
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ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_DIT) \
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)
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/*
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* Restrict to the following *unsigned* features for protected VMs:
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* - AArch64 guests only (no support for AArch32 guests):
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* AArch32 adds complexity in trap handling, emulation, condition codes,
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* etc...
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* - RAS (v1)
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* Supported by KVM
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*/
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#define PVM_ID_AA64PFR0_RESTRICT_UNSIGNED (\
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FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \
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FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL1), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \
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FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL2), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \
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FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL3), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \
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FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_RAS), ID_AA64PFR0_EL1_RAS_IMP) \
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)
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/*
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* Allow for protected VMs:
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* - Branch Target Identification
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* - Speculative Store Bypassing
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*/
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#define PVM_ID_AA64PFR1_ALLOW (\
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ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_BT) | \
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ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SSBS) \
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)
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/*
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* Allow for protected VMs:
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* - Mixed-endian
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* - Distinction between Secure and Non-secure Memory
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* - Mixed-endian at EL0 only
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* - Non-context synchronizing exception entry and exit
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*/
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#define PVM_ID_AA64MMFR0_ALLOW (\
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ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_BIGEND) | \
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ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_SNSMEM) | \
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ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_BIGENDEL0) | \
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ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_EXS) \
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)
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/*
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* Restrict to the following *unsigned* features for protected VMs:
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* - 40-bit IPA
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* - 16-bit ASID
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*/
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#define PVM_ID_AA64MMFR0_RESTRICT_UNSIGNED (\
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FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_PARANGE), ID_AA64MMFR0_EL1_PARANGE_40) | \
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FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_ASIDBITS), ID_AA64MMFR0_EL1_ASIDBITS_16) \
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)
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/*
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* Allow for protected VMs:
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* - Hardware translation table updates to Access flag and Dirty state
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* - Number of VMID bits from CPU
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* - Hierarchical Permission Disables
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* - Privileged Access Never
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* - SError interrupt exceptions from speculative reads
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* - Enhanced Translation Synchronization
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*/
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#define PVM_ID_AA64MMFR1_ALLOW (\
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ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_HAFDBS) | \
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ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_VMIDBits) | \
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ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_HPDS) | \
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ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_PAN) | \
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ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_SpecSEI) | \
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ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_ETS) \
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)
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/*
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* Allow for protected VMs:
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* - Common not Private translations
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* - User Access Override
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* - IESB bit in the SCTLR_ELx registers
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* - Unaligned single-copy atomicity and atomic functions
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* - ESR_ELx.EC value on an exception by read access to feature ID space
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* - TTL field in address operations.
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* - Break-before-make sequences when changing translation block size
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* - E0PDx mechanism
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*/
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#define PVM_ID_AA64MMFR2_ALLOW (\
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ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_CnP) | \
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ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_UAO) | \
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ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_IESB) | \
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ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_AT) | \
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ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_IDS) | \
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ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_TTL) | \
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ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_BBM) | \
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ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_E0PD) \
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)
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/*
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* No support for Scalable Vectors for protected VMs:
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* Requires additional support from KVM, e.g., context-switching and
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* trapping at EL2
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*/
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#define PVM_ID_AA64ZFR0_ALLOW (0ULL)
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/*
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* No support for debug, including breakpoints, and watchpoints for protected
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* VMs:
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* The Arm architecture mandates support for at least the Armv8 debug
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* architecture, which would include at least 2 hardware breakpoints and
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* watchpoints. Providing that support to protected guests adds
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* considerable state and complexity. Therefore, the reserved value of 0 is
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* used for debug-related fields.
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*/
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#define PVM_ID_AA64DFR0_ALLOW (0ULL)
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#define PVM_ID_AA64DFR1_ALLOW (0ULL)
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/*
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* No support for implementation defined features.
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*/
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#define PVM_ID_AA64AFR0_ALLOW (0ULL)
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#define PVM_ID_AA64AFR1_ALLOW (0ULL)
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/*
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* No restrictions on instructions implemented in AArch64.
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*/
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#define PVM_ID_AA64ISAR0_ALLOW (\
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ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_AES) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SHA1) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SHA2) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_CRC32) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_ATOMIC) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_RDM) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SHA3) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SM3) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SM4) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_DP) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_FHM) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_TS) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_TLB) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_RNDR) \
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)
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#define PVM_ID_AA64ISAR1_ALLOW (\
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ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_DPB) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_JSCVT) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_FCMA) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_LRCPC) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_FRINTTS) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_SB) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_SPECRES) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_BF16) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_DGH) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_I8MM) \
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)
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#define PVM_ID_AA64ISAR2_ALLOW (\
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ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) \
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)
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extern struct memblock_region kvm_nvhe_sym(hyp_memory)[];
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extern unsigned int kvm_nvhe_sym(hyp_memblock_nr);
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@@ -1,205 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2021 Google LLC
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* Author: Fuad Tabba <tabba@google.com>
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*/
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#ifndef __ARM64_KVM_FIXED_CONFIG_H__
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#define __ARM64_KVM_FIXED_CONFIG_H__
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#include <asm/sysreg.h>
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/*
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* This file contains definitions for features to be allowed or restricted for
|
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* guest virtual machines, depending on the mode KVM is running in and on the
|
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* type of guest that is running.
|
||||
*
|
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* The ALLOW masks represent a bitmask of feature fields that are allowed
|
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* without any restrictions as long as they are supported by the system.
|
||||
*
|
||||
* The RESTRICT_UNSIGNED masks, if present, represent unsigned fields for
|
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* features that are restricted to support at most the specified feature.
|
||||
*
|
||||
* If a feature field is not present in either, than it is not supported.
|
||||
*
|
||||
* The approach taken for protected VMs is to allow features that are:
|
||||
* - Needed by common Linux distributions (e.g., floating point)
|
||||
* - Trivial to support, e.g., supporting the feature does not introduce or
|
||||
* require tracking of additional state in KVM
|
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* - Cannot be trapped or prevent the guest from using anyway
|
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*/
|
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|
||||
/*
|
||||
* Allow for protected VMs:
|
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* - Floating-point and Advanced SIMD
|
||||
* - Data Independent Timing
|
||||
*/
|
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#define PVM_ID_AA64PFR0_ALLOW (\
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ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_FP) | \
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ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AdvSIMD) | \
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ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_DIT) \
|
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)
|
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|
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/*
|
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* Restrict to the following *unsigned* features for protected VMs:
|
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* - AArch64 guests only (no support for AArch32 guests):
|
||||
* AArch32 adds complexity in trap handling, emulation, condition codes,
|
||||
* etc...
|
||||
* - RAS (v1)
|
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* Supported by KVM
|
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*/
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#define PVM_ID_AA64PFR0_RESTRICT_UNSIGNED (\
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FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \
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FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL1), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \
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FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL2), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \
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FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL3), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \
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FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_RAS), ID_AA64PFR0_EL1_RAS_IMP) \
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)
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|
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/*
|
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* Allow for protected VMs:
|
||||
* - Branch Target Identification
|
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* - Speculative Store Bypassing
|
||||
*/
|
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#define PVM_ID_AA64PFR1_ALLOW (\
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ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_BT) | \
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ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SSBS) \
|
||||
)
|
||||
|
||||
/*
|
||||
* Allow for protected VMs:
|
||||
* - Mixed-endian
|
||||
* - Distinction between Secure and Non-secure Memory
|
||||
* - Mixed-endian at EL0 only
|
||||
* - Non-context synchronizing exception entry and exit
|
||||
*/
|
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#define PVM_ID_AA64MMFR0_ALLOW (\
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ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_BIGEND) | \
|
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ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_SNSMEM) | \
|
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ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_BIGENDEL0) | \
|
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ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_EXS) \
|
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)
|
||||
|
||||
/*
|
||||
* Restrict to the following *unsigned* features for protected VMs:
|
||||
* - 40-bit IPA
|
||||
* - 16-bit ASID
|
||||
*/
|
||||
#define PVM_ID_AA64MMFR0_RESTRICT_UNSIGNED (\
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FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_PARANGE), ID_AA64MMFR0_EL1_PARANGE_40) | \
|
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FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_ASIDBITS), ID_AA64MMFR0_EL1_ASIDBITS_16) \
|
||||
)
|
||||
|
||||
/*
|
||||
* Allow for protected VMs:
|
||||
* - Hardware translation table updates to Access flag and Dirty state
|
||||
* - Number of VMID bits from CPU
|
||||
* - Hierarchical Permission Disables
|
||||
* - Privileged Access Never
|
||||
* - SError interrupt exceptions from speculative reads
|
||||
* - Enhanced Translation Synchronization
|
||||
*/
|
||||
#define PVM_ID_AA64MMFR1_ALLOW (\
|
||||
ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_HAFDBS) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_VMIDBits) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_HPDS) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_PAN) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_SpecSEI) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_ETS) \
|
||||
)
|
||||
|
||||
/*
|
||||
* Allow for protected VMs:
|
||||
* - Common not Private translations
|
||||
* - User Access Override
|
||||
* - IESB bit in the SCTLR_ELx registers
|
||||
* - Unaligned single-copy atomicity and atomic functions
|
||||
* - ESR_ELx.EC value on an exception by read access to feature ID space
|
||||
* - TTL field in address operations.
|
||||
* - Break-before-make sequences when changing translation block size
|
||||
* - E0PDx mechanism
|
||||
*/
|
||||
#define PVM_ID_AA64MMFR2_ALLOW (\
|
||||
ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_CnP) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_UAO) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_IESB) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_AT) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_IDS) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_TTL) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_BBM) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_E0PD) \
|
||||
)
|
||||
|
||||
/*
|
||||
* No support for Scalable Vectors for protected VMs:
|
||||
* Requires additional support from KVM, e.g., context-switching and
|
||||
* trapping at EL2
|
||||
*/
|
||||
#define PVM_ID_AA64ZFR0_ALLOW (0ULL)
|
||||
|
||||
/*
|
||||
* No support for debug, including breakpoints, and watchpoints for protected
|
||||
* VMs:
|
||||
* The Arm architecture mandates support for at least the Armv8 debug
|
||||
* architecture, which would include at least 2 hardware breakpoints and
|
||||
* watchpoints. Providing that support to protected guests adds
|
||||
* considerable state and complexity. Therefore, the reserved value of 0 is
|
||||
* used for debug-related fields.
|
||||
*/
|
||||
#define PVM_ID_AA64DFR0_ALLOW (0ULL)
|
||||
#define PVM_ID_AA64DFR1_ALLOW (0ULL)
|
||||
|
||||
/*
|
||||
* No support for implementation defined features.
|
||||
*/
|
||||
#define PVM_ID_AA64AFR0_ALLOW (0ULL)
|
||||
#define PVM_ID_AA64AFR1_ALLOW (0ULL)
|
||||
|
||||
/*
|
||||
* No restrictions on instructions implemented in AArch64.
|
||||
*/
|
||||
#define PVM_ID_AA64ISAR0_ALLOW (\
|
||||
ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_AES) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SHA1) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SHA2) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_CRC32) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_ATOMIC) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_RDM) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SHA3) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SM3) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SM4) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_DP) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_FHM) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_TS) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_TLB) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_RNDR) \
|
||||
)
|
||||
|
||||
#define PVM_ID_AA64ISAR1_ALLOW (\
|
||||
ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_DPB) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_JSCVT) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_FCMA) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_LRCPC) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_FRINTTS) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_SB) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_SPECRES) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_BF16) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_DGH) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_I8MM) \
|
||||
)
|
||||
|
||||
#define PVM_ID_AA64ISAR2_ALLOW (\
|
||||
ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3) | \
|
||||
ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) \
|
||||
)
|
||||
|
||||
u64 pvm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id);
|
||||
bool kvm_handle_pvm_sysreg(struct kvm_vcpu *vcpu, u64 *exit_code);
|
||||
bool kvm_handle_pvm_restricted(struct kvm_vcpu *vcpu, u64 *exit_code);
|
||||
int kvm_check_pvm_sysreg_table(void);
|
||||
|
||||
#endif /* __ARM64_KVM_FIXED_CONFIG_H__ */
|
||||
@@ -65,4 +65,9 @@ struct pkvm_hyp_vcpu *pkvm_load_hyp_vcpu(pkvm_handle_t handle,
|
||||
unsigned int vcpu_idx);
|
||||
void pkvm_put_hyp_vcpu(struct pkvm_hyp_vcpu *hyp_vcpu);
|
||||
|
||||
u64 pvm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id);
|
||||
bool kvm_handle_pvm_sysreg(struct kvm_vcpu *vcpu, u64 *exit_code);
|
||||
bool kvm_handle_pvm_restricted(struct kvm_vcpu *vcpu, u64 *exit_code);
|
||||
int kvm_check_pvm_sysreg_table(void);
|
||||
|
||||
#endif /* __ARM64_KVM_NVHE_PKVM_H__ */
|
||||
|
||||
@@ -6,7 +6,6 @@
|
||||
|
||||
#include <linux/kvm_host.h>
|
||||
#include <linux/mm.h>
|
||||
#include <nvhe/fixed_config.h>
|
||||
#include <nvhe/mem_protect.h>
|
||||
#include <nvhe/memory.h>
|
||||
#include <nvhe/pkvm.h>
|
||||
|
||||
@@ -11,7 +11,6 @@
|
||||
#include <asm/kvm_pkvm.h>
|
||||
|
||||
#include <nvhe/early_alloc.h>
|
||||
#include <nvhe/fixed_config.h>
|
||||
#include <nvhe/gfp.h>
|
||||
#include <nvhe/memory.h>
|
||||
#include <nvhe/mem_protect.h>
|
||||
|
||||
@@ -26,8 +26,8 @@
|
||||
#include <asm/debug-monitors.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
#include <nvhe/fixed_config.h>
|
||||
#include <nvhe/mem_protect.h>
|
||||
#include <nvhe/pkvm.h>
|
||||
|
||||
/* Non-VHE specific context */
|
||||
DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data);
|
||||
|
||||
@@ -11,7 +11,7 @@
|
||||
|
||||
#include <hyp/adjust_pc.h>
|
||||
|
||||
#include <nvhe/fixed_config.h>
|
||||
#include <nvhe/pkvm.h>
|
||||
|
||||
#include "../../sys_regs.h"
|
||||
|
||||
|
||||
Reference in New Issue
Block a user