arm64: dts: rockchip: rk3568: add opp-table for npu

Change-Id: Ia2e7aadda6c0049003d3c715c0217b3731ffa6a1
Signed-off-by: Liang Chen <cl@rock-chips.com>
This commit is contained in:
Liang Chen
2021-01-11 09:21:57 +08:00
committed by Tao Huang
parent 7441599a38
commit 8b764766dc

View File

@@ -954,15 +954,56 @@
compatible = "rockchip,rknpu";
reg = <0x0 0xfde40000 0x0 0x10000>;
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_NPU>, <&cru ACLK_NPU>, <&cru HCLK_NPU>;
clock-names = "clk", "aclk", "hclk";
clocks = <&scmi_clk 2>, <&cru CLK_NPU>, <&cru ACLK_NPU>, <&cru HCLK_NPU>;
clock-names = "scmi_clk", "clk", "aclk", "hclk";
assigned-clocks = <&cru CLK_NPU>;
assigned-clock-rates = <600000000>;
power-domains = <&power RK3568_PD_NPU>;
operating-points-v2 = <&npu_opp_table>;
iommus = <&rknpu_mmu>;
status = "disabled";
};
npu_opp_table: npu-opp-table {
compatible = "operating-points-v2";
nvmem-cells = <&npu_leakage>;
nvmem-cell-names = "leakage";
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <825000 825000 1000000>;
};
opp-300000000 {
opp-hz = /bits/ 64 <297000000>;
opp-microvolt = <825000 825000 1000000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <825000 825000 1000000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <594000000>;
opp-microvolt = <825000 825000 1000000>;
};
opp-700000000 {
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <825000 825000 1000000>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <875000 875000 1000000>;
};
opp-900000000 {
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <925000 925000 1000000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <1000000 1000000 1000000>;
};
};
rknpu_mmu: iommu@fde4b000 {
compatible = "rockchip,iommu-v2";
reg = <0x0 0xfde4b000 0x0 0x40>;