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arm64: dts: rockchip: rk3562: remove vop vp1 supported

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Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I21cec7ea48db09b3ae64b9d1a9559d50dea8aa91
This commit is contained in:
Sandy Huang
2023-03-10 10:11:59 +08:00
committed by Tao Huang
parent 0b6e89f8ed
commit 8c52cd4de3
12 changed files with 9 additions and 100 deletions
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4
arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-lvds.dts
View File

@@ -91,10 +91,6 @@
status = "okay";
};
&lvds_in_vp1 {
status = "disabled";
};
&pinctrl {
lcd {
lcd_rst_gpio: lcd-rst-gpio {

4
arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-mcu-k350c4516t.dts
View File

@@ -212,10 +212,6 @@
status = "okay";
};
&rgb_in_vp1 {
status = "disabled";
};
/*
* The pins of sai0/vcc_mipicsi0 and rgb are multiplexed
*/

4
arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-rgb-FX070-DHM11BOE-A.dts
View File

@@ -106,10 +106,6 @@
status = "okay";
};
&rgb_in_vp1 {
status = "disabled";
};
&route_rgb {
status = "okay";
connect = <&vp0_out_rgb>;

4
arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-rgb2lvds.dts
View File

@@ -94,10 +94,6 @@
status = "okay";
};
&rgb_in_vp1 {
status = "disabled";
};
&pwm9 {
pinctrl-names = "active";
pinctrl-0 = <&pwm9m0_pins>;

4
arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi
View File

@@ -278,10 +278,6 @@
status = "okay";
};
&dsi_in_vp1 {
status = "disabled";
};
&dsi_panel {
power-supply = <&vcc3v3_lcd_n>;
reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;

12
arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10-sii9022-bt1120-to-hdmi.dts
View File

@@ -15,14 +15,10 @@
};
&dsi {
status = "okay";
status = "disabled";
};
&dsi_in_vp0 {
status = "okay";
};
&dsi_in_vp1 {
status = "disabled";
};
@@ -100,13 +96,9 @@
};
&rgb_in_vp0 {
status = "disabled";
};
&rgb_in_vp1 {
status = "okay";
};
&video_phy {
status = "okay";
status = "disabled";
};

4
arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dtsi
View File

@@ -193,10 +193,6 @@
status = "okay";
};
&dsi_in_vp1 {
status = "disabled";
};
&dsi_panel {
power-supply = <&vcc3v3_lcd_n>;
reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;

4
arch/arm64/boot/dts/rockchip/rk3562-iotest-lp3-v10.dts
View File

@@ -465,10 +465,6 @@
status = "okay";
};
&dsi_in_vp1 {
status = "disabled";
};
&dsi_panel {
power-supply = <&vcc3v3_lcd_n>;
reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;

4
arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts
View File

@@ -522,10 +522,6 @@
status = "okay";
};
&dsi_in_vp1 {
status = "disabled";
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";

4
arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dtsi
View File

@@ -181,10 +181,6 @@
status = "okay";
};
&dsi_in_vp1 {
status = "disabled";
};
&dsi_panel {
power-supply = <&vcc3v3_lcd_n>;
reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;

4
arch/arm64/boot/dts/rockchip/rk3562-test2-ddr4-v10.dtsi
View File

@@ -67,10 +67,6 @@
status = "okay";
};
&dsi_in_vp1 {
status = "disabled";
};
&gmac0 {
/* Use rgmii-rxid mode to disable rx delay inside Soc */
phy-mode = "rmii";

57
arch/arm64/boot/dts/rockchip/rk3562.dtsi
View File

@@ -425,7 +425,7 @@
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
charge_logo,mode = "center";
connect = <&vp1_out_rgb>;
connect = <&vp0_out_rgb>;
};
};
};
@@ -998,12 +998,6 @@
remote-endpoint = <&vp0_out_lvds>;
status = "disabled";
};
lvds_in_vp1: endpoint@1 {
reg = <1>;
remote-endpoint = <&vp1_out_lvds>;
status = "disabled";
};
};
};
};
@@ -1038,12 +1032,6 @@
remote-endpoint = <&vp0_out_rgb>;
status = "disabled";
};
rgb_in_vp1: endpoint@1 {
reg = <1>;
remote-endpoint = <&vp1_out_rgb>;
status = "disabled";
};
};
};
};
@@ -1635,25 +1623,21 @@
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP>,
<&cru HCLK_VOP>,
<&cru DCLK_VOP>,
<&cru DCLK_VOP1>;
<&cru DCLK_VOP>;
clock-names = "aclk_vop",
"hclk_vop",
"dclk_vp0",
"dclk_vp1";
"dclk_vp0";
resets = <&cru SRST_A_VOP>,
<&cru SRST_H_VOP>,
<&cru SRST_D_VOP>,
<&cru SRST_D_VOP1>;
<&cru SRST_D_VOP>;
reset-names = "axi",
"ahb",
"dclk_vp0",
"dclk_vp1";
"dclk_vp0";
iommus = <&vop_mmu>;
power-domains = <&power RK3562_PD_VO>;
rockchip,grf = <&ioc_grf>;
assigned-clocks = <&cru DCLK_VOP>, <&cru DCLK_VOP1>;
assigned-clock-parents = <&cru PLL_VPLL>, <&cru PLL_APLL>;
assigned-clocks = <&cru DCLK_VOP>;
assigned-clock-parents = <&cru PLL_VPLL>;
status = "disabled";
vop_out: ports {
@@ -1680,27 +1664,6 @@
remote-endpoint = <&lvds_in_vp0>;
};
};
vp1: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vp1_out_rgb: endpoint@0 {
reg = <0>;
remote-endpoint = <&rgb_in_vp1>;
};
vp1_out_dsi: endpoint@1 {
reg = <1>;
remote-endpoint = <&dsi_in_vp1>;
};
vp1_out_lvds: endpoint@2 {
reg = <2>;
remote-endpoint = <&lvds_in_vp1>;
};
};
};
};
@@ -2641,12 +2604,6 @@
remote-endpoint = <&vp0_out_dsi>;
status = "disabled";
};
dsi_in_vp1: endpoint@1 {
reg = <1>;
remote-endpoint = <&vp1_out_dsi>;
status = "disabled";
};
};
};
};