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arm64: dts: rockchip: rk3588: add mipi dcphy dts nodes

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Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: I68b0de9bb0ddf00a171754adaae3d2dffd789d2c
This commit is contained in:
Guochun Huang
2021-10-25 08:52:54 +00:00
parent a939cdfe9d
commit 8cc47fe067
1 changed files with 40 additions and 0 deletions
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40
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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@@ -468,6 +468,16 @@
reg = <0x0 0xfd5e0000 0x0 0x100>;
};
mipidcphy0_grf: syscon@fd5e8000 {
compatible = "rockchip,mipi-dcphy-grf", "syscon";
reg = <0x0 0xfd5e8000 0x0 0x4000>;
};
mipidcphy1_grf: syscon@fd5ec000 {
compatible = "rockchip,mipi-dcphy-grf", "syscon";
reg = <0x0 0xfd5ec000 0x0 0x4000>;
};
ioc: syscon@fd5f0000 {
compatible = "rockchip,rk3588-ioc", "syscon";
reg = <0x0 0xfd5f0000 0x0 0x10000>;
@@ -2278,6 +2288,36 @@
};
};
mipi_dcphy0: phy@feda0000 {
compatible = "rockchip,rk3588-mipi-dcphy";
reg = <0x0 0xfeda0000 0x0 0x10000>;
rockchip,grf = <&mipidcphy0_grf>;
clocks = <&cru PCLK_MIPI_DCPHY0>,
<&cru CLK_USBDPPHY_MIPIDCPPHY_REF>;
clock-names = "pclk", "ref";
resets = <&cru SRST_M_MIPI_DCPHY0>,
<&cru SRST_P_MIPI_DCPHY0>,
<&cru SRST_P_MIPI_DCPHY0_GRF>;
reset-names = "phy", "apb", "grf";
#phy-cells = <0>;
status = "disabled";
};
mipi_dcphy1: phy@fedb0000 {
compatible = "rockchip,rk3588-mipi-dcphy";
reg = <0x0 0xfedb0000 0x0 0x10000>;
rockchip,grf = <&mipidcphy1_grf>;
clocks = <&cru PCLK_MIPI_DCPHY1>,
<&cru CLK_USBDPPHY_MIPIDCPPHY_REF>;
clock-names = "pclk", "ref";
resets = <&cru SRST_M_MIPI_DCPHY1>,
<&cru SRST_P_MIPI_DCPHY1>,
<&cru SRST_P_MIPI_DCPHY1_GRF>;
reset-names = "phy", "apb", "grf";
#phy-cells = <0>;
status = "disabled";
};
combphy0_ps: phy@fee00000 {
compatible = "rockchip,rk3588-naneng-combphy";
reg = <0x0 0xfee00000 0x0 0x100>;