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clk: rockchip: rk1808: export SCLK_32K_IOE clock id

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Add clk_32k_ioe to select 32k io as input or output.

Change-Id: Id1d32b913e9739c4462eab6e565b3fcac370e531
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2019-03-07 14:52:15 +08:00
committed by Tao Huang
parent da355404b3
commit 8d550430b6
2 changed files with 6 additions and 0 deletions
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5
drivers/clk/rockchip/clk-rk1808.c
View File

@@ -11,6 +11,7 @@
#include "clk.h"
#define RK1808_GRF_SOC_STATUS0 0x480
#define RK1808_PMUGRF_SOC_CON0 0x100
#define RK1808_UART_FRAC_MAX_PRATE 800000000
#define RK1808_PDM_FRAC_MAX_PRATE 300000000
#define RK1808_I2S_FRAC_MAX_PRATE 600000000
@@ -177,6 +178,7 @@ PNAME(mux_mipidsiphy_ref_p) = { "xin24m", "clk_ref24m_pmu" };
PNAME(mux_pciephy_ref_p) = { "xin24m", "clk_pciephy_src" };
PNAME(mux_ppll_xin24m_p) = { "ppll", "xin24m" };
PNAME(mux_xin24m_32k_p) = { "xin24m", "xin32k" };
PNAME(mux_clk_32k_ioe_p) = { "clk_rtc32k_pmu", "xin32k" };
static struct rockchip_pll_clock rk1808_pll_clks[] __initdata = {
[apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p,
@@ -1139,6 +1141,9 @@ static struct rockchip_clk_branch rk1808_clk_branches[] __initdata = {
GATE(PCLK_UART0_PMU, "pclk_uart0_pmu", "pclk_pmu_pre", 0, RK1808_PMU_CLKGATE_CON(0), 7, GFLAGS),
GATE(0, "pclk_cru_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK1808_PMU_CLKGATE_CON(0), 8, GFLAGS),
GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_pre", 0, RK1808_PMU_CLKGATE_CON(0), 9, GFLAGS),
MUXPMUGRF(SCLK_32K_IOE, "clk_32k_ioe", mux_clk_32k_ioe_p, 0,
RK1808_PMUGRF_SOC_CON0, 0, 1, MFLAGS)
};
static const char *const rk1808_critical_clocks[] __initconst = {

1
include/dt-bindings/clock/rk1808-cru.h
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@@ -111,6 +111,7 @@
#define SCLK_MIPIDSIPHY_REF 110
#define SCLK_PCIEPHY_REF 111
#define SCLK_RTC32K_FRAC 112
#define SCLK_32K_IOE 113
/* aclk gates */
#define ACLK_GIC_PRE 145