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vpu: update vpu_clk_gate control for g12a

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PD#156734: vpu: update vpu_clk_gate control for g12a

Change-Id: Ia0d2bce8ea0e6951a435fc236e4b82bbd32ebcca
Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>
This commit is contained in:
Evoke Zhang
2018-02-11 17:06:12 +08:00
committed by Yixun Lan
parent 9fc3e6cb44
commit 8d8181d96e
2 changed files with 33 additions and 2 deletions
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4
drivers/amlogic/media/common/vpu/vpu.c
View File

@@ -1316,9 +1316,9 @@ static struct vpu_data_s vpu_data_g12a = {
.mem_pd_table_cnt =
sizeof(vpu_mem_pd_g12a) / sizeof(struct vpu_ctrl_s),
.clk_gate_table_cnt =
sizeof(vpu_clk_gate_gxl) / sizeof(struct vpu_ctrl_s),
sizeof(vpu_clk_gate_g12a) / sizeof(struct vpu_ctrl_s),
.mem_pd_table = vpu_mem_pd_g12a,
.clk_gate_table = vpu_clk_gate_gxl,
.clk_gate_table = vpu_clk_gate_g12a,
.power_on = vpu_power_on_txlx,
.power_off = vpu_power_off_txlx,

31
drivers/amlogic/media/common/vpu/vpu_ctrl.h
View File

@@ -390,6 +390,37 @@ static struct vpu_ctrl_s vpu_clk_gate_axg[] = {
{VPU_MAX, VPU_REG_END, 0, 0},
};
static struct vpu_ctrl_s vpu_clk_gate_g12a[] = {
/* vpu module, reg, bit, len */
{VPU_VPU_TOP, VPU_CLK_GATE, 1, 1}, /* vpu_system_clk */
{VPU_VPU_CLKB, VPU_CLK_GATE, 18, 1},
{VPU_RDMA, VPU_CLK_GATE, 15, 1}, /* rdma_clk */
{VPU_VLOCK, VPU_CLK_GATE, 14, 1},
{VPU_MISC, VPU_CLK_GATE, 6, 1}, /* hs,vs interrupt*/
{VPU_VENCP, VPU_CLK_GATE, 3, 1},
{VPU_VENCP, VPU_CLK_GATE, 0, 1},
{VPU_VENCL, VPU_CLK_GATE, 4, 2},
{VPU_VENCI, VPU_CLK_GATE, 10, 2},
{VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 24, 6},
{VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 4, 18},
{VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 1, 1},
{VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL2, 0, 4},
{VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 24, 6},
{VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 4, 18},
{VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 1, 1},
{VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL2, 0, 4},
{VPU_DI, DI_CLKG_CTRL, 26, 5},
{VPU_DI, DI_CLKG_CTRL, 24, 1},
{VPU_DI, DI_CLKG_CTRL, 17, 5},
{VPU_DI, DI_CLKG_CTRL, 0, 2},
{VPU_VPP, VPP_GCLK_CTRL0, 2, 30},
{VPU_VPP, VPP_GCLK_CTRL1, 0, 12},
{VPU_VPP, VPP_SC_GCLK_CTRL, 18, 8},
{VPU_VPP, VPP_SC_GCLK_CTRL, 2, 10},
{VPU_VPP, VPP_XVYCC_GCLK_CTRL, 0, 18},
{VPU_MAX, VPU_REG_END, 0, 0},
};
/* ************************************************ */
#endif