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drm/rockchip: vop: add support mcu register config

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For px30 and rk3308

Change-Id: Ic19bfb871207c778842531a170eb92792139e862
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
This commit is contained in:
Sandy Huang
2018-03-12 17:30:13 +08:00
committed by Tao Huang
parent 4da6b9253e
commit 8db42d7949
3 changed files with 50 additions and 1 deletions
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20
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View File

@@ -235,6 +235,20 @@ struct vop_ctrl {
struct vop_reg st2084oetf_post_conv_en;
struct vop_reg win_csc_mode_sel;
/* MCU OUTPUT */
struct vop_reg mcu_pix_total;
struct vop_reg mcu_cs_pst;
struct vop_reg mcu_cs_pend;
struct vop_reg mcu_rw_pst;
struct vop_reg mcu_rw_pend;
struct vop_reg mcu_clk_sel;
struct vop_reg mcu_hold_mode;
struct vop_reg mcu_frame_st;
struct vop_reg mcu_rs;
struct vop_reg mcu_bypass;
struct vop_reg mcu_type;
struct vop_reg mcu_rw_bypass_port;
struct vop_reg reg_done_frm;
struct vop_reg cfg_done;
};
@@ -361,6 +375,12 @@ enum _vop_rgb2rgb_conv_mode {
BT2020_TO_BT709,
};
enum _MCU_IOCTL {
MCU_WRCMD = 0,
MCU_WRDATA,
MCU_SETBYPASS,
};
struct vop_win_phy {
const struct vop_scl_regs *scl;
const uint32_t *data_formats;

28
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
View File

@@ -1481,6 +1481,20 @@ static const struct vop_ctrl px30_ctrl_data = {
.cabc_stage_down = VOP_REG(PX30_CABC_CTRL2, 0xff, 0),
.cabc_global_dn = VOP_REG(PX30_CABC_CTRL3, 0xff, 0),
.cabc_global_dn_limit_en = VOP_REG(PX30_CABC_CTRL3, 0x1, 8),
.mcu_pix_total = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 0),
.mcu_cs_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 6),
.mcu_cs_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 10),
.mcu_rw_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 16),
.mcu_rw_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 20),
.mcu_clk_sel = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 26),
.mcu_hold_mode = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 27),
.mcu_frame_st = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 28),
.mcu_rs = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 29),
.mcu_bypass = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 30),
.mcu_type = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 31),
.mcu_rw_bypass_port = VOP_REG(RK3366_LIT_MCU_RW_BYPASS_PORT,
0xffffffff, 0),
};
static const struct vop_win_phy px30_win23_data = {
@@ -1583,6 +1597,20 @@ static const struct vop_ctrl rk3308_ctrl_data = {
.bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20),
.bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0),
.bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16),
.mcu_pix_total = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 0),
.mcu_cs_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 6),
.mcu_cs_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 10),
.mcu_rw_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 16),
.mcu_rw_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 20),
.mcu_clk_sel = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 26),
.mcu_hold_mode = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 27),
.mcu_frame_st = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 28),
.mcu_rs = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 29),
.mcu_bypass = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 30),
.mcu_type = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 31),
.mcu_rw_bypass_port = VOP_REG(RK3366_LIT_MCU_RW_BYPASS_PORT,
0xffffffff, 0),
};
static const struct vop_data rk3308_vop = {

3
drivers/gpu/drm/rockchip/rockchip_vop_reg.h
View File

@@ -953,7 +953,7 @@
#define RK3366_LIT_REG_CFG_DONE 0x00000
#define RK3366_LIT_VERSION 0x00004
#define RK3366_LIT_DSP_BG 0x00008
#define RK3366_LIT_MCU_RESERVED 0x0000c
#define RK3366_LIT_MCU_CTRL 0x0000c
#define RK3366_LIT_SYS_CTRL0 0x00010
#define RK3366_LIT_SYS_CTRL1 0x00014
#define RK3366_LIT_SYS_CTRL2 0x00018
@@ -1006,6 +1006,7 @@
#define RK3366_LIT_FRC_LOWER10_1 0x0017c
#define RK3366_LIT_FRC_LOWER11_0 0x00180
#define RK3366_LIT_FRC_LOWER11_1 0x00184
#define RK3366_LIT_MCU_RW_BYPASS_PORT 0x0018c
#define RK3366_LIT_DBG_REG_000 0x00190
#define RK3366_LIT_BLANKING_VALUE 0x001f4
#define RK3366_LIT_FLAG_REG_FRM_VALID 0x001f8