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* commit 'dc2c85b45d99c0ee3af5e9b4e4ee8b16f114785b': (38 commits)
  arm64: dts: rockchip: rv1126b: add debug node
  ARM: configs: rv1126b: Move debug config to evb
  clk: rockchip: rv1126b: add sclk_ddr
  crypto: rockchip: rkce: fix asym NULL point reference
  arm64: dts: rockchip: rv1126b: Add clocks pd vdo
  arm64: dts: rockchip: rv1126b-evb-cam-csi0: add gc8613
  ARM: configs: rv1126b-evb: Enable CONFIG_VIDEO_GC8613
  media: rockchip: vpss: 1126b online scale add new chn ckg_dis
  media: rockchip: vpss: fix online rockit no ch4_ch5
  arm64: dts: rockchip: rv1126b: Set spi0 and spi1 num-cs 2
  arm64: dts: rockchip: rv1126b-evb: enable fspi0
  arm64: dts: rockchip: rv1126b: fix aiisp power domain status is error
  clk: rockchip: rv1126b: add CLK_IS_CRITICAL for hclk_vi_root/pclk_vi_root/pclk_pmu_hp_timer
  media: i2c: add gc8613 sensor driver
  arm64: dts: rockchip: rv1126b: Change to OS_REG8 for reboot
  video: rockchip: rga3: fix match core error in rotate mode
  net: phy: rockchip-fephy: Change 100M amplitude
  arm64: dts: rockchip: rv1126b-evb: Use 50M clkin for macphy
  ethernet: stmmac: dwmac-rk: Use 50M clkin sel for macphy
  media: i2c: sc450ai: Increase vblank of 2688x1520@30fps configuration
  ...

Change-Id: I385563b87cfbe4cc466ddd2a85fde2b0853dbae7
This commit is contained in:
Tao Huang
2025-03-31 16:49:19 +08:00
parent e36de9374c dc2c85b45d
commit 8e08df3eee
36 changed files with 3526 additions and 292 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
arch/arm/configs/rv1126b-evb.config
View File

@@ -7,6 +7,7 @@ CONFIG_EXPORTFS_BLOCK_OPS=y
CONFIG_EXT4_FS=y
CONFIG_EXTCON=y
CONFIG_FILE_LOCKING=y
CONFIG_HARDLOCKUP_DETECTOR=y
CONFIG_I2C_GPIO=y
CONFIG_I2C_MUX=y
CONFIG_INPUT=y
@@ -22,6 +23,8 @@ CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NVMEM_SYSFS=y
CONFIG_PANIC_ON_OOPS=y
CONFIG_PANIC_ON_OOPS_VALUE=1
CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
CONFIG_RK_CMA_PROCFS=y
CONFIG_RK_DMABUF_PROCFS=y
@@ -34,11 +37,13 @@ CONFIG_SND_SOC_RK817=y
CONFIG_SND_SOC_RK_DSM=y
CONFIG_SND_SOC_ROCKCHIP_ASRC=y
CONFIG_SND_SOC_ROCKCHIP_PDM_V2=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_SPI=y
CONFIG_USB_SUPPORT=y
CONFIG_VFAT_FS=y
CONFIG_VIDEOBUF2_DMA_SG=y
CONFIG_VIDEO_GC2053=m
CONFIG_VIDEO_GC8613=m
CONFIG_VIDEO_IMX415=m
CONFIG_VIDEO_OS04A10=m
# CONFIG_VIDEO_RK_IRCUT is not set
@@ -136,6 +141,8 @@ CONFIG_BLK_DEBUG_FS=y
# CONFIG_BMC150_MAGN_SPI is not set
# CONFIG_BMI088_ACCEL is not set
# CONFIG_BMI160_SPI is not set
CONFIG_BOOTPARAM_HARDLOCKUP_PANIC=y
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
# CONFIG_BSD_DISKLABEL is not set
# CONFIG_CEPH_FS is not set
CONFIG_CFG80211=m
@@ -311,6 +318,7 @@ CONFIG_FS_POSIX_ACL=y
# CONFIG_GPIO_XRA1403 is not set
CONFIG_GRACE_PERIOD=y
# CONFIG_GUP_TEST is not set
CONFIG_HARDLOCKUP_DETECTOR_OTHER_CPU=y
# CONFIG_HI8435 is not set
# CONFIG_HID is not set
# CONFIG_HID_PID is not set
@@ -420,6 +428,7 @@ CONFIG_KEYBOARD_ADC=y
# CONFIG_LMK04832 is not set
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_LOCKUP_DETECTOR=y
# CONFIG_LOCK_EVENT_COUNTS is not set
# CONFIG_LTC1660 is not set
# CONFIG_LTC2496 is not set

5
arch/arm/configs/rv1126b_defconfig
View File

@@ -213,11 +213,6 @@ CONFIG_PRINTK_TIME_FROM_ARM_ARCH_TIMER=y
# CONFIG_DEBUG_MISC is not set
CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
# CONFIG_SLUB_DEBUG is not set
CONFIG_PANIC_ON_OOPS=y
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
CONFIG_HARDLOCKUP_DETECTOR=y
CONFIG_BOOTPARAM_HARDLOCKUP_PANIC=y
# CONFIG_DETECT_HUNG_TASK is not set
# CONFIG_SCHED_DEBUG is not set
# CONFIG_RCU_TRACE is not set
# CONFIG_FTRACE is not set

54
arch/arm64/boot/dts/rockchip/rv1126b-evb-cam-csi0.dtsi
View File

@@ -38,6 +38,18 @@
remote-endpoint = <&tp2815_out>;
data-lanes = <1 2 3 4>;
};
csi_dphy_input4: endpoint@5 {
reg = <5>;
remote-endpoint = <&imx327_out>;
data-lanes = <4>;
};
csi_dphy_input5: endpoint@6 {
reg = <5>;
remote-endpoint = <&gc8613_out>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
@@ -56,6 +68,27 @@
status = "okay";
pinctrl-0 = <&i2c3m1_pins>;
imx327: imx327@1a {
compatible = "sony,imx327";
reg = <0x1a>;
clocks = <&cru CLK_MIPI0_OUT2IO>;
clock-names = "xvclk";
reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&cam_clk0_pins>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
port {
imx327_out: endpoint {
remote-endpoint = <&csi_dphy_input4>;
bus-type = <3>;
data-lanes = <4>;
};
};
};
imx415: imx415@1a {
compatible = "sony,imx415";
reg = <0x1a>;
@@ -120,6 +153,27 @@
};
};
gc8613: gc8613@31 {
compatible = "galaxycore,gc8613";
reg = <0x31>;
clocks = <&cru CLK_MIPI0_OUT2IO>;
clock-names = "xvclk";
reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&cam_clk0_pins>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
port {
gc8613_out: endpoint {
remote-endpoint = <&csi_dphy_input5>;
data-lanes = <1 2 3 4>;
};
};
};
tp2815: tp2815@44 {
compatible = "techpoint,tp2815";
status = "okay";

15
arch/arm64/boot/dts/rockchip/rv1126b-evb1-v10.dts
View File

@@ -78,6 +78,7 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-low;
regulator-boot-on; // The legacy U-Boot GPIO driver needs this to set correct SDMMC0_PWREN value
vin-supply = <&vcc12v_dcin>;
};
@@ -177,6 +178,18 @@
status = "okay";
};
&fspi0 {
status = "okay";
flash@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <75000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
};
};
&gmac {
phy-mode = "rmii";
clock_in_out = "input";
@@ -318,7 +331,7 @@
compatible = "ethernet-phy-id0680.8101", "ethernet-phy-ieee802.3-c22";
reg = <2>;
clocks = <&cru CLK_MACPHY>;
clock-frequency = <24000000>;
clock-frequency = <50000000>;
resets = <&cru SRST_RESETN_MACPHY>;
pinctrl-names = "default";
pinctrl-0 = <&fephym1_pins>;

15
arch/arm64/boot/dts/rockchip/rv1126b-evb3-v10.dts
View File

@@ -159,6 +159,18 @@
cpu-supply = <&vdd_cpu>;
};
&fspi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <100000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
};
};
&rkaiisp {
status = "okay";
};
@@ -184,14 +196,17 @@
};
&pwm1_4ch_0 {
pinctrl-0 = <&pwm1m2_ch0_pins>;
status = "okay";
};
&pwm1_4ch_1 {
pinctrl-0 = <&pwm1m2_ch1_pins>;
status = "okay";
};
&pwm1_4ch_2 {
pinctrl-0 = <&pwm1m2_ch2_pins>;
status = "okay";
};

2
arch/arm64/boot/dts/rockchip/rv1126b-iotest-v10.dts
View File

@@ -129,7 +129,7 @@
compatible = "ethernet-phy-id0680.8101", "ethernet-phy-ieee802.3-c22";
reg = <2>;
clocks = <&cru CLK_MACPHY>;
clock-frequency = <24000000>;
clock-frequency = <50000000>;
resets = <&cru SRST_RESETN_MACPHY>;
phy-is-integrated;
};

22
arch/arm64/boot/dts/rockchip/rv1126b.dtsi
View File

@@ -826,7 +826,7 @@
reboot_mode: reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x30200>;
offset = <0x30220>;
mode-bootloader = <BOOT_BL_DOWNLOAD>;
mode-charge = <BOOT_CHARGING>;
mode-fastboot = <BOOT_FASTBOOT>;
@@ -1484,6 +1484,7 @@
<&shaping_rkvdec>,
<&shaping_rkjpeg>,
<&shaping_decom>;
clocks = <&cru ACLK_RKVDEC_ROOT>;
rockchip,always-on;
};
power-domain@RV1126B_PD_AISP {
@@ -2305,6 +2306,7 @@
clock-names = "spiclk", "apb_pclk";
dmas = <&dmac 40>, <&dmac 41>;
dma-names = "rx", "tx";
num-cs = <2>;
pinctrl-names = "default";
pinctrl-0 = <&spi0m0_clk_pins &spi0m0_csn0_pins &spi0m0_csn1_pins>;
status = "disabled";
@@ -2320,6 +2322,7 @@
clock-names = "spiclk", "apb_pclk";
dmas = <&dmac 42>, <&dmac 43>;
dma-names = "rx", "tx";
num-cs = <2>;
pinctrl-names = "default";
pinctrl-0 = <&spi1m0_clk_pins &spi1m0_csn0_pins &spi1m0_csn1_pins>;
status = "disabled";
@@ -2994,12 +2997,12 @@
interrupt-names = "irq_rkvenc";
clocks = <&cru ACLK_VEPU>, <&cru HCLK_VEPU>, <&cru CLK_CORE_VEPU>;
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
rockchip,normal-rates = <396000000>, <0>, <396000000>;
rockchip,normal-rates = <396000000>, <0>, <550000000>;
resets = <&cru SRST_ARESETN_VEPU>, <&cru SRST_HRESETN_VEPU>,
<&cru SRST_RESETN_CORE_VEPU>;
reset-names = "video_a", "video_h", "video_core";
assigned-clocks = <&cru ACLK_VEPU>, <&cru CLK_CORE_VEPU>;
assigned-clock-rates = <396000000>, <396000000>;
assigned-clock-rates = <396000000>, <550000000>;
iommus = <&rkvenc_mmu>;
rockchip,srv = <&mpp_srv>;
rockchip,taskqueue-node = <0>;
@@ -3101,8 +3104,9 @@
reg = <0x21fa3f00 0x100>;
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "aiisp_mmu";
clocks = <&cru ACLK_AISP>, <&cru HCLK_AISP>;
clock-names = "aclk", "iface";
clocks = <&cru ACLK_AISP>, <&cru HCLK_AISP>,
<&cru CLK_CORE_AISP>;
clock-names = "aclk_aiisp", "hclk_aiisp", "clk_aiisp_core";
power-domains = <&power RV1126B_PD_AISP>;
rockchip,disable-mmu-reset;
#iommu-cells = <0>;
@@ -3338,6 +3342,14 @@
status = "disabled";
};
debug: debug@22410000 {
compatible = "rockchip,debug";
reg = <0x22410000 0x1000>,
<0x22510000 0x1000>,
<0x22610000 0x1000>,
<0x22710000 0x1000>;
};
system_sram: sram@3ffb0000 {
compatible = "mmio-sram";
reg = <0x3ffb0000 0x10000>;

34
arch/arm64/boot/dts/rockchip/rv1126bp-evb-v14.dts
View File

@@ -6,7 +6,7 @@
/dts-v1/;
#include "rv1126b.dtsi"
#include "rv1126bp-evb.dtsi"
#include "rv1126b-evb-cam-csi0.dtsi"
#include "rv1126bp-evb-v14-cam.dtsi"
/ {
model = "Rockchip RV1126B-P EVB V14 Board";
@@ -419,38 +419,6 @@
};
};
&i2c1 {
status = "okay";
pinctrl-0 = <&i2c1m2_pins>;
sc450ai: sc450ai@30{
compatible = "smartsens,sc450ai";
status = "okay";
reg = <0x30>;
clocks = <&cru CLK_MIPI0_OUT2IO>;
clock-names = "xvclk";
reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&cam_clk0_pins>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT2119-PC1";
rockchip,camera-module-lens-name = "30IRC-F16";
port {
sc450ai_out: endpoint {
remote-endpoint = <&csi_dphy_input0>;
data-lanes = <1 2>;
};
};
};
};
&i2c3 {
status = "disabled";
/delete-node/ sc450ai@30;
};
&i2c5 {
pinctrl-0 = <&i2c5m2_pins>;
status = "okay";

15
arch/arm64/configs/rk3576_vehicle.config
View File

@@ -22,7 +22,6 @@ CONFIG_CPU_IDLE_GOV_TEO=y
# CONFIG_CPU_RK3528 is not set
# CONFIG_CPU_RK3562 is not set
# CONFIG_CPU_RK3568 is not set
# CONFIG_CRYPTO_DEV_ROCKCHIP_V1 is not set
# CONFIG_CRYPTO_DEV_ROCKCHIP_V3 is not set
# CONFIG_DRM_MAXIM_MAX96745 is not set
# CONFIG_DRM_MAXIM_MAX96755F is not set
@@ -34,13 +33,15 @@ CONFIG_GPIO_NCA9539=y
# CONFIG_HALL_DEVICE is not set
CONFIG_HZ=1000
CONFIG_HZ_1000=y
# CONFIG_HZ_300 is not set
# CONFIG_HZ_250 is not set
# CONFIG_IIO_ST_LSM6DSR is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_LIGHT_DEVICE is not set
CONFIG_LOG_BUF_SHIFT=20
# CONFIG_MALI400 is not set
# CONFIG_MALI_MIDGARD is not set
# CONFIG_MFD_MAX96745 is not set
# CONFIG_MFD_MAX96755F is not set
# CONFIG_MFD_RK618 is not set
# CONFIG_MFD_RK630_I2C is not set
# CONFIG_MFD_RKX110_X120 is not set
@@ -56,15 +57,9 @@ CONFIG_REALTEK_PHY=y
# CONFIG_REGULATOR_WL2868C is not set
# CONFIG_REGULATOR_XZ3216 is not set
# CONFIG_ROCKCHIP_CHARGER_MANAGER is not set
# CONFIG_ROCKCHIP_CLK_BOOST is not set
# CONFIG_ROCKCHIP_CLK_INV is not set
# CONFIG_ROCKCHIP_CLK_PVTM is not set
# CONFIG_ROCKCHIP_DDRCLK_SIP is not set
# CONFIG_ROCKCHIP_DDRCLK_SIP_V2 is not set
CONFIG_ROCKCHIP_DRM_DIRECT_SHOW=y
# CONFIG_ROCKCHIP_PLL_RK3066 is not set
# CONFIG_ROCKCHIP_PLL_RK3399 is not set
# CONFIG_ROCKCHIP_SERDES_DRM_PANEL is not set
CONFIG_RTC_DRV_S35390A=y
# CONFIG_SLUB_SYSFS is not set
# CONFIG_SND_SOC_AW883XX is not set
@@ -118,9 +113,6 @@ CONFIG_VIDEO_MAXIM_SERDES=y
# CONFIG_VIDEO_RK628_BT1120 is not set
# CONFIG_VIDEO_RK628_CSI is not set
# CONFIG_VIDEO_RK_IRCUT is not set
# CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V1X is not set
# CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V21 is not set
# CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V32 is not set
# CONFIG_VIDEO_S5K3L6XX is not set
# CONFIG_VIDEO_S5KJN1 is not set
# CONFIG_VIDEO_SGM3784 is not set
@@ -141,6 +133,7 @@ CONFIG_SERDES_DISPLAY_CHIP_ROHM=y
CONFIG_SERDES_DISPLAY_CHIP_ROHM_BU18RL82=y
CONFIG_SERDES_DISPLAY_CHIP_ROHM_BU18TL82=y
CONFIG_VIDEO_MAXIM_CAM_DUMMY=y
# CONFIG_VIDEO_MAXIM_CAM_OS04A10 is not set
CONFIG_VIDEO_MAXIM_CAM_OV231X=y
CONFIG_VIDEO_MAXIM_CAM_OX01F10=y
CONFIG_VIDEO_MAXIM_CAM_OX03J10=y

17
arch/arm64/configs/rv1126b_defconfig
View File

@@ -201,7 +201,11 @@ CONFIG_MEDIA_SUPPORT_FILTER=y
# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_PLATFORM_SUPPORT=y
CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=y
# CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV is not set
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_ROCKCHIP_CIF=y
CONFIG_VIDEO_ROCKCHIP_ISP=y
CONFIG_VIDEO_ROCKCHIP_VPSS=y
@@ -221,6 +225,19 @@ CONFIG_BACKLIGHT_PWM=y
CONFIG_ROCKCHIP_MULTI_RGA=y
CONFIG_ROCKCHIP_RGA_PROC_FS=y
# CONFIG_ROCKCHIP_RGA_DEBUG_FS is not set
CONFIG_ROCKCHIP_MPP_SERVICE=y
CONFIG_ROCKCHIP_MPP_RKVDEC=y
CONFIG_ROCKCHIP_MPP_RKVDEC2=y
CONFIG_ROCKCHIP_MPP_RKVENC=y
CONFIG_ROCKCHIP_MPP_RKVENC2=y
CONFIG_ROCKCHIP_MPP_VDPU1=y
CONFIG_ROCKCHIP_MPP_VEPU1=y
CONFIG_ROCKCHIP_MPP_VDPU2=y
CONFIG_ROCKCHIP_MPP_VEPU2=y
CONFIG_ROCKCHIP_MPP_IEP2=y
CONFIG_ROCKCHIP_MPP_JPGDEC=y
CONFIG_ROCKCHIP_MPP_JPGENC=y
CONFIG_ROCKCHIP_MPP_AV1DEC=y
CONFIG_ROCKCHIP_MPP_OSAL=y
CONFIG_SOUND=y
CONFIG_SND=y

3
drivers/clk/rockchip/Kconfig
View File

@@ -214,7 +214,8 @@ config ROCKCHIP_DDRCLK_SIP
config ROCKCHIP_DDRCLK_SIP_V2
bool "Rockchip DDR Clk SIP V2"
depends on CPU_PX30 || CPU_RK1808 || CPU_RK312X || CPU_RK322X || \
CPU_RK3288 || CPU_RK3308 || CPU_RK3328 || CPU_RV1126
CPU_RK3288 || CPU_RK3308 || CPU_RK3328 || CPU_RV1126 || \
CPU_RV1126B
default y
select ROCKCHIP_DDRCLK
help

15
drivers/clk/rockchip/clk-rv1126b.c
View File

@@ -22,7 +22,7 @@
#define PVTPLL_SRC_SEL_PVTPLL (BIT(0) | BIT(16))
enum rv1126b_plls {
gpll, cpll, aupll
gpll, cpll, aupll, dpll
};
static struct rockchip_pll_rate_table rv1126b_pll_rates[] = {
@@ -142,6 +142,7 @@ PNAME(clk_timer2_parents_p) = { "clk_timer_root", "mclk_sai2_from_io", "sclk_sa
PNAME(clk_timer3_parents_p) = { "clk_timer_root", "mclk_asrc0", "mclk_asrc1" };
PNAME(clk_timer4_parents_p) = { "clk_timer_root", "mclk_asrc2", "mclk_asrc3" };
PNAME(clk_macphy_p) = { "xin24m", "clk_cpll_div20" };
PNAME(mux_ddrphy_p) = { "dpll", "aclk_sysmem" };
static struct rockchip_pll_clock rv1126b_pll_clks[] __initdata = {
[gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
@@ -153,6 +154,9 @@ static struct rockchip_pll_clock rv1126b_pll_clks[] __initdata = {
[cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
CLK_IS_CRITICAL, RV1126B_PERIPLL_CON(0),
RV1126B_MODE_CON, 4, 10, 0, rv1126b_pll_rates),
[dpll] = PLL(pll_rk3328, 0, "dpll", mux_pll_p,
CLK_IS_CRITICAL, RV1126B_SUBDDRPLL_CON(0),
RV1126B_MODE_CON, 2, 10, 0, rv1126b_pll_rates),
};
#define MFLAGS CLK_MUX_HIWORD_MASK
@@ -350,9 +354,9 @@ static struct rockchip_clk_branch rv1126b_clk_branches[] __initdata = {
COMPOSITE_NODIV(ACLK_VI_ROOT, "aclk_vi_root", mux_500m_400m_300m_p, CLK_IS_CRITICAL,
RV1126B_CLKSEL_CON(40), 7, 2, MFLAGS,
RV1126B_CLKGATE_CON(6), 2, GFLAGS),
GATE(HCLK_VI_ROOT, "hclk_vi_root", "clk_gpll_div8", 0,
GATE(HCLK_VI_ROOT, "hclk_vi_root", "clk_gpll_div8", CLK_IS_CRITICAL,
RV1126B_CLKGATE_CON(6), 3, GFLAGS),
GATE(PCLK_VI_ROOT, "pclk_vi_root", "clk_cpll_div10", 0,
GATE(PCLK_VI_ROOT, "pclk_vi_root", "clk_cpll_div10", CLK_IS_CRITICAL,
RV1126B_CLKGATE_CON(6), 4, GFLAGS),
COMPOSITE_NODIV(DCLK_VICAP_ROOT, "dclk_vicap_root", mux_333m_200m_p, 0,
RV1126B_CLKSEL_CON(42), 5, 1, MFLAGS,
@@ -692,6 +696,9 @@ static struct rockchip_clk_branch rv1126b_clk_branches[] __initdata = {
RV1126B_VDOCLKGATE_CON(1), 13, GFLAGS),
/* pd_subddr */
COMPOSITE_DDRCLK(SCLK_DDR, "sclk_ddr", mux_ddrphy_p, CLK_GET_RATE_NOCACHE,
RV1126B_SUBDDRCLKSEL_CON(1), 1, 1, 0, 1,
ROCKCHIP_DDRCLK_SIP_V2),
/* pd_ddr */
GATE(PCLK_DDRC, "pclk_ddrc", "pclk_ddr_root", CLK_IS_CRITICAL,
@@ -729,7 +736,7 @@ static struct rockchip_clk_branch rv1126b_clk_branches[] __initdata = {
COMPOSITE_NODIV(DBCLK_PMU_GPIO0, "dbclk_pmu_gpio0", mux_24m_32k_p, 0,
RV1126B_PMUCLKSEL_CON(2), 4, 1, MFLAGS,
RV1126B_PMUCLKGATE_CON(0), 8, GFLAGS),
GATE(PCLK_PMU_HP_TIMER, "pclk_pmu_hp_timer", "busclk_pmu_root", 0,
GATE(PCLK_PMU_HP_TIMER, "pclk_pmu_hp_timer", "busclk_pmu_root", CLK_IS_CRITICAL,
RV1126B_PMUCLKGATE_CON(0), 10, GFLAGS),
COMPOSITE(CLK_PMU_HP_TIMER, "clk_pmu_hp_timer", mux_cpll_24m_p, CLK_IS_CRITICAL,
RV1126B_PMUCLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS,

77
drivers/crypto/rockchip/rkce/rkce_akcipher.c
View File

@@ -22,6 +22,8 @@
#include "rkce_sm2signature.asn1.h"
#include "rkce_ecdsasignature.asn1.h"
static DEFINE_MUTEX(akcipher_mutex);
static void rkce_rsa_adjust_rsa_key(struct rsa_key *key)
{
if (key->n_sz && key->n && !key->n[0]) {
@@ -131,32 +133,8 @@ static int rkce_rsa_setprivkey(struct crypto_akcipher *tfm, const void *key,
return rkce_rsa_setkey(tfm, key, keylen, true);
}
static int rkce_rsa_handle_req(struct akcipher_request *req, bool encrypt)
static int rkce_rsa_calc(struct akcipher_request *req, bool encrypt)
{
struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req);
struct rkce_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
struct crypto_engine *engine = ctx->algt->rk_dev->asym_engine;
rk_trace("enter.\n");
ctx->is_enc = encrypt;
return crypto_transfer_akcipher_request_to_engine(engine, req);
}
static int rkce_rsa_enc(struct akcipher_request *req)
{
return rkce_rsa_handle_req(req, true);
}
static int rkce_rsa_dec(struct akcipher_request *req)
{
return rkce_rsa_handle_req(req, false);
}
static int rkce_rsa_run_req(struct crypto_engine *engine, void *async_req)
{
struct akcipher_request *req = container_of(async_req, struct akcipher_request, base);
struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req);
struct rkce_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
struct rkce_bignum *in = NULL, *out = NULL;
@@ -169,7 +147,7 @@ static int rkce_rsa_run_req(struct crypto_engine *engine, void *async_req)
if (unlikely(!ctx->n || !ctx->e))
goto exit;
if (!ctx->is_enc && !ctx->d)
if (!encrypt && !ctx->d)
goto exit;
key_byte_size = rkce_bn_get_size(ctx->n);
@@ -211,11 +189,15 @@ static int rkce_rsa_run_req(struct crypto_engine *engine, void *async_req)
if (ret)
goto exit;
if (ctx->is_enc)
mutex_lock(&akcipher_mutex);
if (encrypt)
ret = rkce_pka_expt_mod(in, ctx->e, ctx->n, out);
else
ret = rkce_pka_expt_mod(in, ctx->d, ctx->n, out);
mutex_unlock(&akcipher_mutex);
if (ret)
goto exit;
@@ -232,8 +214,6 @@ static int rkce_rsa_run_req(struct crypto_engine *engine, void *async_req)
req->dst_len = key_byte_size;
exit:
crypto_finalize_akcipher_request(ctx->algt->rk_dev->asym_engine, req, ret);
kfree(tmp_buf);
rkce_bn_free(in);
@@ -244,6 +224,16 @@ exit:
return ret;
}
static int rkce_rsa_enc(struct akcipher_request *req)
{
return rkce_rsa_calc(req, true);
}
static int rkce_rsa_dec(struct akcipher_request *req)
{
return rkce_rsa_calc(req, false);
}
static int rkce_rsa_init_tfm(struct crypto_akcipher *tfm)
{
struct rkce_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
@@ -258,7 +248,6 @@ static int rkce_rsa_init_tfm(struct crypto_akcipher *tfm)
ctx->algt = algt;
ctx->enginectx.op.do_one_request = rkce_rsa_run_req;
rkce_pka_set_crypto_base(algt->rk_dev->reg);
@@ -343,27 +332,8 @@ int rkce_ecc_get_signature_s(void *context, size_t hdrlen, unsigned char tag,
return rkce_bn_set_data(sig->y, tmp_value, vlen, RK_BG_BIG_ENDIAN);
}
static int rkce_ecc_handle_req(struct akcipher_request *req, bool sign)
{
struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req);
struct rkce_ecc_ctx *ctx = akcipher_tfm_ctx(tfm);
struct crypto_engine *engine = ctx->algt->rk_dev->asym_engine;
rk_trace("enter.\n");
ctx->is_sign = sign;
return crypto_transfer_akcipher_request_to_engine(engine, req);
}
static int rkce_ec_verify(struct akcipher_request *req)
{
return rkce_ecc_handle_req(req, false);
}
static int rkce_ecc_run_req(struct crypto_engine *engine, void *async_req)
{
struct akcipher_request *req = container_of(async_req, struct akcipher_request, base);
struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req);
struct rkce_ecc_ctx *ctx = akcipher_tfm_ctx(tfm);
size_t keylen = ctx->nbits / 8;
@@ -412,10 +382,11 @@ static int rkce_ecc_run_req(struct crypto_engine *engine, void *async_req)
memcpy(&rawhash, buffer + req->src_len, keylen);
}
ret = rkce_ecc_verify(ctx->group_id, rawhash, keylen, ctx->point_Q, sig_point);
exit:
crypto_finalize_akcipher_request(ctx->algt->rk_dev->asym_engine, req, ret);
mutex_lock(&akcipher_mutex);
ret = rkce_ecc_verify(ctx->group_id, rawhash, keylen, ctx->point_Q, sig_point);
mutex_unlock(&akcipher_mutex);
exit:
kfree(buffer);
rkce_ecc_free_point(sig_point);
@@ -489,8 +460,6 @@ static int rkce_ec_init_tfm(struct crypto_akcipher *tfm)
ctx->algt = algt;
ctx->enginectx.op.do_one_request = rkce_ecc_run_req;
ctx->group_id = rkce_ecc_get_group_id(algt->algo);
ctx->nbits = rkce_ecc_get_curve_nbits(ctx->group_id);
ctx->point_Q = rkce_ecc_alloc_point_zero(RK_ECP_MAX_BYTES);

7
drivers/crypto/rockchip/rkce/rkce_dev.c
View File

@@ -321,11 +321,8 @@ static int rkce_probe(struct platform_device *pdev)
rk_dev->hash_engine = crypto_engine_alloc_init(&pdev->dev, true);
crypto_engine_start(rk_dev->hash_engine);
rk_dev->asym_engine = crypto_engine_alloc_init(&pdev->dev, true);
crypto_engine_start(rk_dev->asym_engine);
rk_debug("symm_engine = %p hash_engine = %p asym_engine = %p",
rk_dev->symm_engine, rk_dev->hash_engine, rk_dev->asym_engine);
rk_debug("symm_engine = %p hash_engine = %p",
rk_dev->symm_engine, rk_dev->hash_engine);
rk_cryptodev_register_dev(dev, "RKCE multi");

1
drivers/crypto/rockchip/rkce/rkce_dev.h
View File

@@ -57,7 +57,6 @@ struct rkce_dev {
spinlock_t lock;
struct crypto_engine *symm_engine;
struct crypto_engine *hash_engine;
struct crypto_engine *asym_engine;
void *hardware;
};

47
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
View File

@@ -2690,7 +2690,8 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
global_alpha_en = (vop_plane_state->global_alpha == 0xff) ? 0 : 1;
if ((is_alpha_support(fb->format->format) || global_alpha_en) &&
(s->dsp_layer_sel & 0x3) != win->win_id) {
((vop->version != VOP_VERSION_RV1126B && (s->dsp_layer_sel & 0x3) != win->win_id) ||
(vop->version == VOP_VERSION_RV1126B && (s->dsp_layer_sel & BIT(win->win_id))))) {
int src_blend_m0;
int pre_multi_alpha = ALPHA_SRC_PRE_MUL;
@@ -4510,9 +4511,10 @@ static int vop_crtc_atomic_check(struct drm_crtc *crtc,
struct drm_plane *plane;
struct drm_plane_state *pstate;
struct vop_plane_state *plane_state;
struct vop_zpos *pzpos;
struct vop_zpos *pzpos, *zpos;
const struct vop_win_data *win_data;
int dsp_layer_sel = 0;
int i, j, cnt = 0, ret = 0;
int i, j, cnt = 0, ret = 0, shift;
ret = vop_afbdc_atomic_check(crtc, crtc_state);
if (ret)
@@ -4571,15 +4573,40 @@ static int vop_crtc_atomic_check(struct drm_crtc *crtc,
sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
const struct vop_win_data *win_data = &vop_data->win[i];
int shift = i * 2;
win_data = &vop_data->win[i];
shift = i * 2;
zpos = &pzpos[cnt];
if (win_data->phy) {
struct vop_zpos *zpos = &pzpos[cnt++];
dsp_layer_sel |= zpos->win_id << shift;
/*
* 1. For RV1126B:
* dsp_layer2_sel, that is top layer:
* - 2'b00 WIN0 is top layer
* - 2'b01 WIN2 is top layer
* dsp_layer1_sel, that is bottom layer:
* - 2'b00 WIN0 is bottom layer
* - 2'b01 WIN2 is bottom layer
*
* For {dsp_layer2_sel, dsp_layer1_sel}:
* - 4'b0001 : WIN0 on the top, WIN2 on the bottom
* - 4'b0100 : WIN2 on the top, WIN0 on the bottom
*
* 2. For other version:
* - 2'b00 select WIN0
* - 2'b10 select WIN2
*/
if (vop->version == VOP_VERSION_RV1126B) {
if (win_data->phy) {
/* only set top layer */
if (cnt++)
dsp_layer_sel |= BIT(zpos->win_id);
}
} else {
dsp_layer_sel |= i << shift;
if (win_data->phy) {
cnt++;
dsp_layer_sel |= zpos->win_id << shift;
} else {
dsp_layer_sel |= i << shift;
}
}
}

4
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
View File

@@ -1815,7 +1815,7 @@ static const struct vop_ctrl rv1126_ctrl_data = {
.dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0),
.global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13),
.auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0),
.dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xff, 22),
.dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 22),
.overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4),
.core_dclk_div = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 13),
.dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14),
@@ -1957,7 +1957,7 @@ static const struct vop_ctrl rv1126b_ctrl_data = {
.dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14),
.dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),
.out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16),
.dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xff, 22),
.dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 22),
.color_bar_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xff, 28),
.color_bar_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xff, 31),

13
drivers/media/i2c/Kconfig
View File

@@ -458,6 +458,19 @@ config VIDEO_GC8034
To compile this driver as a module, choose M here: the
module will be called gc8034.
config VIDEO_GC8613
tristate "GalaxyCore GC8613 sensor support"
depends on I2C && VIDEO_DEV
depends on MEDIA_CAMERA_SUPPORT
select MEDIA_CONTROLLER
select VIDEO_V4L2_SUBDEV_API
select V4L2_FWNODE
help
Support for the GalaxyCore GC8613 sensor.
To compile this driver as a module, choose M here: the
module will be called GC8613.
config VIDEO_HI556
tristate "Hynix Hi-556 sensor support"
depends on I2C && VIDEO_DEV

1
drivers/media/i2c/Makefile
View File

@@ -74,6 +74,7 @@ obj-$(CONFIG_VIDEO_GC5024) += gc5024.o
obj-$(CONFIG_VIDEO_GC5025) += gc5025.o
obj-$(CONFIG_VIDEO_GC5035) += gc5035.o
obj-$(CONFIG_VIDEO_GC8034) += gc8034.o
obj-$(CONFIG_VIDEO_GC8613) += gc8613.o
obj-$(CONFIG_VIDEO_HI556) += hi556.o
obj-$(CONFIG_VIDEO_HI846) += hi846.o
obj-$(CONFIG_VIDEO_HI847) += hi847.o

3077
drivers/media/i2c/gc8613.c Normal file
View File

File diff suppressed because it is too large Load Diff

97
drivers/media/i2c/sc450ai.c
View File

@@ -5,6 +5,7 @@
* Copyright (C) 2020 Rockchip Electronics Co., Ltd.
*
* V0.0X01.0X01 first version
* V0.0X01.0X02 Increase vblank in 2688x1520@30fps linear 4lane configuration
*/
//#define DEBUG
@@ -30,18 +31,18 @@
#include "cam-tb-setup.h"
#include "cam-sleep-wakeup.h"
#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01)
#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x02)
#ifndef V4L2_CID_DIGITAL_GAIN
#define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
#endif
#define SC450AI_LANES 2
#define SC450AI_LANES 4
#define SC450AI_BITS_PER_SAMPLE 10
#define SC450AI_LINK_FREQ_360 360000000
#define PIXEL_RATE_WITH_360M_10BIT (SC450AI_LINK_FREQ_360 * 2 * \
SC450AI_LANES / SC450AI_BITS_PER_SAMPLE)
#define PIXEL_RATE_WITH_360M_10BIT (SC450AI_LINK_FREQ_360 / SC450AI_BITS_PER_SAMPLE * 2 * \
SC450AI_LANES)
#define SC450AI_XVCLK_FREQ 27000000
@@ -372,27 +373,26 @@ static const struct regval sc450ai_linear_10_1344x760_120fps_regs[] = {
/*
* Xclk 27Mhz
* max_framerate 60fps
* mipi_datarate per lane 720Mbps, 2lane
* max_framerate 30fps
* mipi_datarate per lane 720Mbps, 4lane
*/
static const struct regval sc450ai_linear_10_2688x1520_30fps_regs[] = {
{0x0103, 0x01},
{0x0100, 0x00},
{0x36e9, 0x80},
{0x36f9, 0x80},
{0x3018, 0x3a},
{0x3019, 0x0c},
{0x301c, 0x78},
{0x301f, 0x3c},
{0x301f, 0x02},
{0x302d, 0xa0},
{0x302e, 0x00},
{0x3208, 0x0a},
{0x3209, 0x80},
{0x320a, 0x05},
{0x320b, 0xf0},
{0x320c, 0x02},
{0x320d, 0xee},
{0x320e, 0x06},
{0x320f, 0x18},
{0x320c, 0x03},
{0x320d, 0xa8},
{0x320e, 0x0c},
{0x320f, 0x30},
{0x3214, 0x11},
{0x3215, 0x11},
{0x3220, 0x00},
@@ -401,38 +401,38 @@ static const struct regval sc450ai_linear_10_2688x1520_30fps_regs[] = {
{0x325f, 0x44},
{0x3274, 0x09},
{0x3280, 0x01},
{0x3301, 0x07},
{0x3306, 0x20},
{0x3308, 0x08},
{0x330b, 0x58},
{0x330e, 0x18},
{0x3301, 0x08},
{0x3306, 0x24},
{0x3309, 0x60},
{0x330b, 0x64},
{0x330d, 0x30},
{0x3315, 0x00},
{0x331f, 0x59},
{0x335d, 0x60},
{0x3364, 0x56},
{0x338f, 0x80},
{0x3390, 0x08},
{0x3391, 0x18},
{0x3392, 0x38},
{0x3393, 0x07},
{0x3393, 0x0a},
{0x3394, 0x10},
{0x3395, 0x18},
{0x3396, 0x08},
{0x3397, 0x18},
{0x3398, 0x38},
{0x3399, 0x10},
{0x339a, 0x13},
{0x339b, 0x15},
{0x3399, 0x0f},
{0x339a, 0x12},
{0x339b, 0x14},
{0x339c, 0x18},
{0x33af, 0x18},
{0x3400, 0x16},
{0x360f, 0x13},
{0x3621, 0xec},
{0x3622, 0x00},
{0x3625, 0x0b},
{0x3627, 0x20},
{0x3627, 0xa0},
{0x3630, 0x90},
{0x3633, 0x56},
{0x3637, 0x1d},
{0x3638, 0x12},
{0x3638, 0x0a},
{0x363c, 0x0f},
{0x363d, 0x0f},
{0x363e, 0x08},
@@ -440,27 +440,27 @@ static const struct regval sc450ai_linear_10_2688x1520_30fps_regs[] = {
{0x3671, 0xe0},
{0x3672, 0xe0},
{0x3673, 0xe0},
{0x3674, 0xc0},
{0x3675, 0x87},
{0x3674, 0xb0},
{0x3675, 0x88},
{0x3676, 0x8c},
{0x367a, 0x48},
{0x367b, 0x58},
{0x367c, 0x48},
{0x367d, 0x58},
{0x3690, 0x22},
{0x3691, 0x33},
{0x3690, 0x34},
{0x3691, 0x43},
{0x3692, 0x44},
{0x3699, 0x03},
{0x369a, 0x0f},
{0x369b, 0x1f},
{0x369c, 0x40},
{0x369d, 0x78},
{0x369d, 0x48},
{0x36a2, 0x48},
{0x36a3, 0x78},
{0x36b0, 0x53},
{0x36b1, 0x74},
{0x36b2, 0x34},
{0x36b3, 0x40},
{0x36b0, 0x54},
{0x36b1, 0x75},
{0x36b2, 0x35},
{0x36b3, 0x48},
{0x36b4, 0x78},
{0x36b7, 0xa0},
{0x36b8, 0xa0},
@@ -473,22 +473,25 @@ static const struct regval sc450ai_linear_10_2688x1520_30fps_regs[] = {
{0x36e2, 0x12},
{0x36e3, 0x48},
{0x36e4, 0x78},
{0x36ec, 0x43},
{0x36fa, 0x0d},
{0x36fb, 0xa4},
{0x36fc, 0x00},
{0x36fd, 0x24},
{0x3907, 0x00},
{0x3908, 0x41},
{0x391e, 0xf1},
{0x391e, 0x01},
{0x391f, 0x11},
{0x3921, 0x10},
{0x3933, 0x82},
{0x3934, 0x30},
{0x3934, 0x0b},
{0x3935, 0x02},
{0x3936, 0xc7},
{0x3936, 0x5e},
{0x3937, 0x76},
{0x3938, 0x76},
{0x3938, 0x78},
{0x3939, 0x00},
{0x393a, 0x28},
{0x393b, 0x00},
{0x393c, 0x23},
{0x393c, 0x1d},
{0x3e01, 0xc2},
{0x3e02, 0x60},
{0x3e03, 0x0b},
@@ -499,6 +502,7 @@ static const struct regval sc450ai_linear_10_2688x1520_30fps_regs[] = {
{0x4837, 0x16},
{0x5000, 0x0e},
{0x5001, 0x44},
{0x5780, 0x76},
{0x5784, 0x08},
{0x5785, 0x04},
{0x5787, 0x0a},
@@ -514,9 +518,12 @@ static const struct regval sc450ai_linear_10_2688x1520_30fps_regs[] = {
{0x5793, 0x08},
{0x5794, 0x04},
{0x5795, 0x04},
{0x5799, 0x06},
{0x57aa, 0x28},
{0x57ab, 0x00},
{0x5799, 0x46},
{0x579a, 0x77},
{0x57a1, 0x04},
{0x57a8, 0xd0},
{0x57aa, 0x2a},
{0x57ab, 0x7f},
{0x57ac, 0x00},
{0x57ad, 0x00},
{0x59e0, 0xfe},
@@ -562,7 +569,7 @@ static const struct sc450ai_mode supported_modes[] = {
},
.exp_def = 0x0080,//mark
.hts_def = 0x2ee * 4,
.vts_def = 0x0618,
.vts_def = 0x0c30,
.bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
.reg_list = sc450ai_linear_10_2688x1520_30fps_regs,
.hdr_mode = NO_HDR,

20
drivers/media/i2c/techpoint/techpoint_v4l2.c
View File

@@ -1356,6 +1356,17 @@ static int techpoint_sysfs_init(struct i2c_client *client,
return 0;
}
static void techpoint_sysfs_cleanup(struct techpoint *techpoint)
{
struct device *dev = &techpoint->dev;
int i;
for (i = 0; i < ARRAY_SIZE(techpoint_attrs); i++)
device_remove_file(dev, &techpoint_attrs[i]);
device_unregister(dev);
}
static int techpoint_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
@@ -1376,13 +1387,8 @@ static int techpoint_probe(struct i2c_client *client,
techpoint->client = client;
techpoint->supplies = NULL;
techpoint_sysfs_init(client, techpoint);
mutex_init(&techpoint->mutex);
sd = &techpoint->subdev;
v4l2_i2c_subdev_init(sd, client, &techpoint_subdev_ops);
techpoint_analyze_dts(techpoint);
ret = __techpoint_power_on(techpoint);
@@ -1397,6 +1403,8 @@ static int techpoint_probe(struct i2c_client *client,
goto err_power_off;
}
sd = &techpoint->subdev;
v4l2_i2c_subdev_init(sd, client, &techpoint_subdev_ops);
ret = techpoint_initialize_controls(techpoint);
if (ret) {
dev_err(dev, "Failed to initialize controls techpoint\n");
@@ -1441,6 +1449,7 @@ static int techpoint_probe(struct i2c_client *client,
goto err_clean_entity;
}
techpoint_sysfs_init(client, techpoint);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
pm_runtime_idle(dev);
@@ -1466,6 +1475,7 @@ static void techpoint_remove(struct i2c_client *client)
struct v4l2_subdev *sd = i2c_get_clientdata(client);
struct techpoint *techpoint = to_techpoint(sd);
techpoint_sysfs_cleanup(techpoint);
v4l2_async_unregister_subdev(sd);
#if defined(CONFIG_MEDIA_CONTROLLER)
media_entity_cleanup(&sd->entity);

15
drivers/media/platform/rockchip/cif/capture.c
View File

@@ -5127,7 +5127,8 @@ static int rkcif_csi_channel_set_rv1126b(struct rkcif_stream *stream,
if (stream->dma_en) {
if (mbus_type == V4L2_MBUS_CSI2_DPHY ||
mbus_type == V4L2_MBUS_CSI2_CPHY) {
mbus_type == V4L2_MBUS_CSI2_CPHY ||
dev->chip_id >= CHIP_RV1126B_CIF) {
dma_en = CSI_DMA_ENABLE_RK3576;
} else {
dma_en = LVDS_DMAEN_RV1106;
@@ -12063,7 +12064,9 @@ static u32 rkcif_get_sof(struct rkcif_device *cif_dev)
struct csi2_dev *csi;
if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY ||
sensor->mbus.type == V4L2_MBUS_CSI2_CPHY) {
sensor->mbus.type == V4L2_MBUS_CSI2_CPHY ||
(sensor->mbus.type == V4L2_MBUS_CCP2 &&
cif_dev->chip_id >= CHIP_RV1106_CIF)) {
csi = container_of(sensor->sd, struct csi2_dev, sd);
val = rkcif_csi2_get_sof(csi);
} else if (sensor->mbus.type == V4L2_MBUS_CCP2) {
@@ -12081,7 +12084,9 @@ void rkcif_set_sof(struct rkcif_device *cif_dev, u32 seq)
struct csi2_dev *csi;
if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY ||
sensor->mbus.type == V4L2_MBUS_CSI2_CPHY) {
sensor->mbus.type == V4L2_MBUS_CSI2_CPHY ||
(sensor->mbus.type == V4L2_MBUS_CCP2 &&
cif_dev->chip_id >= CHIP_RV1106_CIF)) {
csi = container_of(sensor->sd, struct csi2_dev, sd);
rkcif_csi2_set_sof(csi, seq);
} else if (sensor->mbus.type == V4L2_MBUS_CCP2) {
@@ -13139,7 +13144,9 @@ static void rkcif_send_sof(struct rkcif_device *cif_dev)
return;
if (mbus->type == V4L2_MBUS_CSI2_DPHY ||
mbus->type == V4L2_MBUS_CSI2_CPHY) {
mbus->type == V4L2_MBUS_CSI2_CPHY ||
(mbus->type == V4L2_MBUS_CCP2 &&
cif_dev->chip_id >= CHIP_RV1106_CIF)) {
csi = container_of(cif_dev->active_sensor->sd, struct csi2_dev, sd);
rkcif_csi2_event_inc_sof(csi);
} else if (mbus->type == V4L2_MBUS_CCP2) {

9
drivers/media/platform/rockchip/cif/dev.c
View File

@@ -1897,7 +1897,8 @@ static int rkcif_create_link(struct rkcif_device *dev,
linked_sensor.lanes = sensor->lanes;
if (sensor->mbus.type == V4L2_MBUS_CCP2) {
if (sensor->mbus.type == V4L2_MBUS_CCP2 &&
dev->chip_id < CHIP_RV1106_CIF) {
linked_sensor.sd = &dev->lvds_subdev.sd;
dev->lvds_subdev.sensor_self.sd = &dev->lvds_subdev.sd;
dev->lvds_subdev.sensor_self.lanes = sensor->lanes;
@@ -2027,7 +2028,8 @@ static int rkcif_create_link(struct rkcif_device *dev,
}
}
if (sensor->mbus.type == V4L2_MBUS_CCP2) {
if (sensor->mbus.type == V4L2_MBUS_CCP2 &&
dev->chip_id < CHIP_RV1106_CIF) {
source_entity = &sensor->sd->entity;
sink_entity = &linked_sensor.sd->entity;
ret = media_create_pad_link(source_entity,
@@ -2143,7 +2145,8 @@ static int subdev_notifier_complete(struct v4l2_async_notifier *notifier)
sensor->lanes = sensor->mbus.bus.mipi_csi1.data_lane;
}
if (sensor->mbus.type == V4L2_MBUS_CCP2) {
if (sensor->mbus.type == V4L2_MBUS_CCP2 &&
dev->chip_id < CHIP_RV1106_CIF) {
ret = rkcif_register_lvds_subdev(dev);
if (ret < 0) {
v4l2_err(&dev->v4l2_dev,

24
drivers/media/platform/rockchip/cif/mipi-csi2.c
View File

@@ -125,7 +125,7 @@ static void csi2_update_sensor_info(struct csi2_dev *csi2)
csi2->dsi_input_en = 0;
}
csi2->bus = mbus.bus.mipi_csi2;
csi2->mbus = mbus;
}
@@ -172,23 +172,19 @@ static void csi2_disable(struct csi2_hw *csi2_hw)
write_csihost_reg(csi2_hw->base, CSIHOST_MSK2, 0xffffffff);
}
static int csi2_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *mbus);
static void csi2_enable(struct csi2_hw *csi2_hw,
enum host_type_t host_type)
{
void __iomem *base = csi2_hw->base;
struct csi2_dev *csi2 = csi2_hw->csi2;
int lanes = csi2->bus.num_data_lanes;
struct v4l2_mbus_config mbus;
int lanes = csi2->mbus.bus.mipi_csi2.num_data_lanes;
struct v4l2_mbus_config mbus = csi2->mbus;
u32 val = 0;
u32 mask1 = 0;
struct v4l2_subdev *terminal_sensor_sd = NULL;
struct rkmodule_hdr_cfg hdr_cfg = {0};
int ret = 0;
csi2_g_mbus_config(&csi2->sd, 0, &mbus);
if (mbus.type == V4L2_MBUS_CSI2_DPHY)
val = SW_CPHY_EN(0);
else if (mbus.type == V4L2_MBUS_CSI2_CPHY)
@@ -248,6 +244,10 @@ static int csi2_start(struct csi2_dev *csi2)
csi2_update_sensor_info(csi2);
if (csi2->mbus.type != V4L2_MBUS_CSI2_DPHY &&
csi2->mbus.type != V4L2_MBUS_CSI2_CPHY)
return 0;
if (csi2->dsi_input_en == RKMODULE_DSI_INPUT)
host_type = RK_DSI_RXHOST;
else
@@ -295,6 +295,10 @@ static void csi2_stop(struct csi2_dev *csi2)
int i = 0;
int csi_idx = 0;
if (csi2->mbus.type != V4L2_MBUS_CSI2_DPHY &&
csi2->mbus.type != V4L2_MBUS_CSI2_CPHY)
return;
/* stop upstream */
v4l2_subdev_call(csi2->src_sd, video, s_stream, 0);
@@ -415,7 +419,7 @@ static int csi2_media_init(struct v4l2_subdev *sd)
csi2->crop.left = 0;
csi2->crop.width = RKCIF_DEFAULT_WIDTH;
csi2->crop.height = RKCIF_DEFAULT_HEIGHT;
csi2->bus.num_data_lanes = 4;
csi2->mbus.bus.mipi_csi2.num_data_lanes = 4;
return media_entity_pads_init(&sd->entity, num_pads, csi2->pad);
}
@@ -536,8 +540,8 @@ static int csi2_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
ret = v4l2_subdev_call(sensor_sd, pad, get_mbus_config, 0, mbus);
if (ret) {
mbus->type = V4L2_MBUS_CSI2_DPHY;
mbus->bus.mipi_csi2.flags = csi2->bus.flags;
mbus->bus.mipi_csi2.flags |= BIT(csi2->bus.num_data_lanes - 1);
mbus->bus.mipi_csi2.flags = csi2->mbus.bus.mipi_csi2.flags;
mbus->bus.mipi_csi2.flags |= BIT(csi2->mbus.bus.mipi_csi2.num_data_lanes - 1);
}
return 0;

2
drivers/media/platform/rockchip/cif/mipi-csi2.h
View File

@@ -152,7 +152,7 @@ struct csi2_dev {
void __iomem *base;
struct v4l2_async_notifier notifier;
struct v4l2_mbus_config_mipi_csi2 bus;
struct v4l2_mbus_config mbus;
/* lock to protect all members below */
struct mutex lock;

13
drivers/media/platform/rockchip/vpss/stream_v20.c
View File

@@ -1629,6 +1629,9 @@ static void bilinear_scale(struct rkvpss_stream *stream, bool on, bool sync)
/*config scl clk gate*/
switch (stream->id) {
case RKVPSS_OUTPUT_CH0:
clk_mask = RKVPSS_SCL0_CKG_DIS;
break;
case RKVPSS_OUTPUT_CH1:
clk_mask = RKVPSS_SCL1_CKG_DIS;
break;
@@ -1638,6 +1641,12 @@ static void bilinear_scale(struct rkvpss_stream *stream, bool on, bool sync)
case RKVPSS_OUTPUT_CH3:
clk_mask = RKVPSS_SCL3_CKG_DIS;
break;
case RKVPSS_OUTPUT_CH4:
clk_mask = RKVPSS2X_SCL4_CKG_DIS;
break;
case RKVPSS_OUTPUT_CH5:
clk_mask = RKVPSS2X_SCL5_CKG_DIS;
break;
default:
return;
}
@@ -1849,8 +1858,8 @@ static int rkvpss_stream_scale(struct rkvpss_stream *stream, bool on, bool sync)
if ((stream->id == 0 || stream->id == 2) && stream->avg_scl_down)
average_scale_down(stream, on, sync);
bilinear_scale(stream, on, sync);
else
bilinear_scale(stream, on, sync);
return 0;
}

6
drivers/media/platform/rockchip/vpss/vpss_rockit.c
View File

@@ -73,6 +73,12 @@ static struct rkvpss_stream *rkvpss_rockit_get_stream(struct rockit_rkvpss_cfg *
case 3:
stream = &vpss_dev->stream_vdev.stream[RKVPSS_OUTPUT_CH3];
break;
case 4:
stream = &vpss_dev->stream_vdev.stream[RKVPSS_OUTPUT_CH4];
break;
case 5:
stream = &vpss_dev->stream_vdev.stream[RKVPSS_OUTPUT_CH5];
break;
default:
stream = NULL;
break;

52
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
View File

@@ -71,6 +71,7 @@ struct rk_priv_data {
struct clk *clk_phy;
struct clk *pclk_xpcs;
struct clk *clk_xpcs_eee;
unsigned int clk_phy_rate;
struct reset_control *phy_reset;
@@ -2556,6 +2557,9 @@ static const struct rk_gmac_ops rv1126_ops = {
#define RV1126B_RK_MACPHY_DISABLE 0
#define RV1126B_RK_MACPHY_ENABLE BIT(31)
#define RV1126B_RK_MACPHY_CLK_24M 0
#define RV1126B_RK_MACPHY_CLK_50M BIT(11)
static void rv1126b_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
{
@@ -2589,6 +2593,10 @@ static void rv1126b_set_to_rmii(struct rk_priv_data *bsp_priv)
return;
}
if (bsp_priv->integrated_phy)
regmap_write(bsp_priv->grf, RV1126B_VI_GRF_GMAC_CON0,
RV1126B_GMAC_RK_MACPHY_ENABLE);
regmap_write(bsp_priv->grf, RV1126B_VI_GRF_GMAC_CON0,
RV1126B_GMAC_PHY_INTF_SEL_RMII |
RV1126B_GMAC_CLK_RMII_DIV2);
@@ -2664,23 +2672,34 @@ static void rv1126b_integrated_phy_power(struct rk_priv_data *priv, bool up)
}
if (up) {
unsigned int value;
regmap_write(priv->grf, RV1126B_VI_GRF_RK_MACPHY_CON1,
RV1126B_RK_MACPHY_DISABLE);
reset_control_assert(priv->phy_reset);
usleep_range(10, 20);
regmap_write(priv->grf, RV1126B_VI_GRF_GMAC_CON0,
RV1126B_GMAC_RK_MACPHY_ENABLE);
usleep_range(20, 40);
if (priv->clk_phy_rate == 50000000)
regmap_write(priv->grf, RV1126B_VI_GRF_RK_MACPHY_CON2,
RV1126B_RK_MACPHY_CLK_50M);
else
regmap_write(priv->grf, RV1126B_VI_GRF_RK_MACPHY_CON2,
RV1126B_RK_MACPHY_CLK_24M);
regmap_write(priv->grf, RV1126B_VI_GRF_RK_MACPHY_CON0,
RV1126B_RK_MACPHY_PHY_ID | RV1126B_RK_MACPHY_PHY_ADDR);
regmap_write(priv->grf, RV1126B_VI_GRF_RK_MACPHY_CON1,
RV1126B_RK_MACPHY_PHY_REVISION |
RV1126B_RK_MACPHY_PHY_MODEL |
RV1126B_RK_MACPHY_ENABLE);
usleep_range(110, 120);
value = RV1126B_RK_MACPHY_PHY_REVISION | RV1126B_RK_MACPHY_PHY_MODEL |
RV1126B_RK_MACPHY_ENABLE;
regmap_write(priv->grf, RV1126B_VI_GRF_RK_MACPHY_CON1, value);
usleep_range(200, 220);
reset_control_deassert(priv->phy_reset);
regmap_write(priv->grf, RV1126B_VI_GRF_RK_MACPHY_CON1,
RV1126B_RK_MACPHY_DISABLE);
usleep_range(100, 120);
regmap_write(priv->grf, RV1126B_VI_GRF_RK_MACPHY_CON1, value);
} else {
regmap_write(priv->grf, RV1126B_VI_GRF_RK_MACPHY_CON1,
RV1126B_RK_MACPHY_DISABLE);
regmap_write(priv->grf, RV1126B_VI_GRF_GMAC_CON0,
RV1126B_GMAC_RK_MACPHY_DISABLE);
}
}
@@ -2764,22 +2783,17 @@ static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0);
/* If it is not integrated_phy, clk_phy is optional */
if (bsp_priv->integrated_phy) {
unsigned int rate = 0;
if (IS_ERR(bsp_priv->clk_phy)) {
ret = PTR_ERR(bsp_priv->clk_phy);
dev_err(dev, "Cannot get PHY clock: %d\n", ret);
return -EINVAL;
} else {
ret = of_property_read_u32(plat->phy_node, "clock-frequency", &rate);
ret = of_property_read_u32(plat->phy_node, "clock-frequency",
&bsp_priv->clk_phy_rate);
if (ret)
rate = 0;
bsp_priv->clk_phy_rate = 50000000;
}
if (rate)
clk_set_rate(bsp_priv->clk_phy, rate);
else
clk_set_rate(bsp_priv->clk_phy, 50000000);
clk_set_rate(bsp_priv->clk_phy, bsp_priv->clk_phy_rate);
}
}

8
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
View File

@@ -356,8 +356,8 @@ int stmmac_mdio_idle(struct mii_bus *bus)
reset_gpio = devm_gpiod_get_optional(priv->device,
"snps,reset",
GPIOD_OUT_HIGH);
if (IS_ERR(reset_gpio))
return PTR_ERR(reset_gpio);
if (IS_ERR_OR_NULL(reset_gpio))
return PTR_ERR_OR_ZERO(reset_gpio);
devm_gpiod_put(priv->device, reset_gpio);
}
@@ -386,8 +386,8 @@ int stmmac_mdio_reset(struct mii_bus *bus)
reset_gpio = devm_gpiod_get_optional(priv->device,
"snps,reset",
GPIOD_OUT_LOW);
if (IS_ERR(reset_gpio))
return PTR_ERR(reset_gpio);
if (IS_ERR_OR_NULL(reset_gpio))
return PTR_ERR_OR_ZERO(reset_gpio);
device_property_read_u32_array(priv->device,
"snps,reset-delays-us",

79
drivers/net/phy/rockchip-fephy.c
View File

@@ -62,6 +62,31 @@ struct rockchip_fephy_priv {
int wol_irq;
};
static int rockchip_fephy_init_tstmode(struct phy_device *phydev)
{
int ret;
ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE);
if (ret)
return ret;
ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE);
if (ret)
return ret;
ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE);
if (ret)
return ret;
return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE);
}
static int rockchip_fephy_close_tstmode(struct phy_device *phydev)
{
/* Back to basic register bank */
return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE);
}
static int rockchip_fephy_bank_write(struct phy_device *phydev, u8 bank,
u32 reg, u16 val)
{
@@ -83,54 +108,24 @@ static int rockchip_fephy_config_init(struct phy_device *phydev)
if (ret)
return ret;
/* AUTO MDI/X */
phydev->mdix = ETH_TP_MDI_AUTO;
ret = rockchip_fephy_init_tstmode(phydev);
if (ret)
return ret;
/* 100M amplitude control */
ret = rockchip_fephy_bank_write(phydev, BANK_DSP0, 0x18, 0xc);
if (ret)
return ret;
ret = rockchip_fephy_close_tstmode(phydev);
if (ret)
return ret;
return ret;
}
static int rockchip_fephy_set_polarity(struct phy_device *phydev, int polarity)
{
int reg, err, val;
/* get the current settings */
reg = phy_read(phydev, MII_INTERNAL_CTRL_STATUS);
if (reg < 0)
return reg;
val = reg;
val &= ~MII_AUTO_MDIX_EN;
switch (polarity) {
case ETH_TP_MDI:
val &= ~MII_MDIX_EN;
break;
case ETH_TP_MDI_X:
val |= MII_MDIX_EN;
break;
case ETH_TP_MDI_AUTO:
case ETH_TP_MDI_INVALID:
default:
return 0;
}
if (val != reg) {
/* Set the new polarity value in the register */
err = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val);
if (err)
return err;
}
return 0;
}
static int rockchip_fephy_config_aneg(struct phy_device *phydev)
{
int err;
err = rockchip_fephy_set_polarity(phydev, phydev->mdix);
if (err < 0)
return err;
return genphy_config_aneg(phydev);
}

2
drivers/phy/rockchip/phy-rockchip-csi2-dphy-hw.c
View File

@@ -84,7 +84,7 @@
#define CSI2_DPHY_PATH1_LVDS_MODE_SEL (0x880)
/* rv1126b path mode */
#define RV1126B_CSI2_DPHY_PATH0_MODE_SEL (0x66C)
#define RV1126B_CSI2_DPHY_PATH0_MODE_SEL (0x6CC)
#define RV1126B_CSI2_DPHY_PATH0_LVDS_MODE_SEL (0x700)
#define RV1126B_CSI2_DPHY_PATH1_MODE_SEL (0xACC)
#define RV1126B_CSI2_DPHY_PATH1_LVDS_MODE_SEL (0xB00)

8
drivers/regulator/rk806-regulator.c
View File

@@ -1180,7 +1180,7 @@ static int __maybe_unused rk806_suspend(struct device *dev)
{
struct rk806 *rk806 = dev_get_drvdata(dev->parent);
struct rk806_platform_data *pdata = rk806->pdata;
int value;
int value, chip_ver;
int i;
rk806_field_write(rk806, RST_FUN, 0x00);
@@ -1216,7 +1216,11 @@ static int __maybe_unused rk806_suspend(struct device *dev)
if (pdata->dvs_control_suspend[i] == CTR_BY_PWRCTRL3)
rk806_field_write(rk806, PWRCTRL3_FUN, PWRCTRL_DVS_FUN);
}
rk806_field_write(rk806, PWRCTRL1_FUN, PWRCTRL_SLP_FUN);
chip_ver = rk806_field_read(rk806, CHIP_VER);
if (chip_ver & 0x08)
rk806_field_write(rk806, PWRCTRL1_FUN, PWRCTRL_SLP_FUN);
else
rk806_field_write(rk806, PWRCTRL1_FUN, PWRCTRL_DVS_FUN);
}
return 0;

2
drivers/soc/rockchip/rockchip_decompress_user.c
View File

@@ -57,7 +57,7 @@ static bool check_scatter_list(unsigned int max_size, struct sg_table *sg_tbl)
return false;
for_each_sgtable_sg(sg_tbl, sgl, i) {
if (sg_phys(sgl) > SZ_4G || sg_phys(sgl) + sg_dma_len(sgl) > SZ_4G)
if (sg_phys(sgl) >= SZ_4G || sg_phys(sgl) + sg_dma_len(sgl) > SZ_4G)
return false;
if (i && next_addr != sg_dma_address(sgl))

11
drivers/video/rockchip/mpp/mpp_jpgdec.c
View File

@@ -485,15 +485,6 @@ static int jpgdec_set_freq(struct mpp_dev *mpp,
return 0;
}
static int jpgdec_reduce_freq(struct mpp_dev *mpp)
{
struct jpgdec_dev *dec = to_jpgdec_dev(mpp);
mpp_clk_set_rate(&dec->aclk_info, CLK_MODE_REDUCE);
return 0;
}
static int jpgdec_irq(struct mpp_dev *mpp)
{
u32 clr_mask = 0;
@@ -578,7 +569,7 @@ static struct mpp_hw_ops jpgdec_v1_hw_ops = {
.clk_on = jpgdec_clk_on,
.clk_off = jpgdec_clk_off,
.set_freq = jpgdec_set_freq,
.reduce_freq = jpgdec_reduce_freq,
.reduce_freq = NULL,
.reset = jpgdec_reset,
};

37
drivers/video/rockchip/rga3/rga_policy.c
View File

@@ -174,8 +174,9 @@ static bool rga_check_align(struct rga_job *job,
static bool rga_check_channel(struct rga_job *job, const struct rga_hw_data *data,
struct rga_img_info_t *img,
const char *name, int input, int win_num)
const char *name, int input, int swap, int win_num)
{
int w, h;
const struct rga_rect_range *range;
if (input)
@@ -183,28 +184,36 @@ static bool rga_check_channel(struct rga_job *job, const struct rga_hw_data *dat
else
range = &data->output_range;
if (!rga_check_resolution(range, img->act_w, img->act_h)) {
if (swap) {
w = img->act_h;
h = img->act_w;
} else {
w = img->act_w;
h = img->act_h;
}
if (!rga_check_resolution(range, w, h)) {
if (DEBUGGER_EN(MSG))
rga_job_log(job, "%s resolution check error, input range[%dx%d ~ %dx%d], [w,h] = [%d, %d]\n",
name,
data->input_range.min.width, data->input_range.min.height,
data->input_range.max.width, data->input_range.max.height,
img->act_w, img->act_h);
w, h);
return false;
}
if (data == &rga3_data &&
!rga_check_resolution(&data->input_range,
img->act_w + img->x_offset,
img->act_h + img->y_offset)) {
w + img->x_offset,
h + img->y_offset)) {
if (DEBUGGER_EN(MSG))
rga_job_log(job, "%s RGA3 resolution check error, input range[%dx%d ~ %dx%d], [w+x,h+y] = [%d, %d]\n",
name,
data->input_range.min.width, data->input_range.min.height,
data->input_range.max.width, data->input_range.max.height,
img->act_w + img->x_offset,
img->act_h + img->y_offset);
w + img->x_offset,
h + img->y_offset);
return false;
}
@@ -303,6 +312,7 @@ int rga_job_assign(struct rga_job *job)
int i;
int min_of_job_count = -1;
unsigned long flags;
int need_swap = false;
/* assigned by userspace */
if (rga_base->core > RGA_NONE_CORE) {
@@ -345,6 +355,13 @@ int rga_job_assign(struct rga_job *job)
}
}
/* some mode rotate 90/270 need swap dst_width/dst_height */
if (((rga_base->rotate_mode & 0x0f) == 1) &&
((rga_base->sina == 65536 && rga_base->cosa == 0) ||
(rga_base->sina == -65536 && rga_base->cosa == 0))) {
need_swap = true;
}
/* only colorfill need single win (colorpalette?) */
if (!(feature & 1)) {
if (src1->yrgb_addr > 0) {
@@ -407,7 +424,7 @@ int rga_job_assign(struct rga_job *job)
continue;
}
if (!rga_check_channel(job, data, src0, "src0", true, 0)) {
if (!rga_check_channel(job, data, src0, "src0", true, false, 0)) {
if (DEBUGGER_EN(MSG))
rga_job_log(job, "%s(%#x), break on src0",
rga_get_core_name(scheduler->core),
@@ -416,7 +433,7 @@ int rga_job_assign(struct rga_job *job)
}
if (src1->yrgb_addr > 0) {
if (!rga_check_channel(job, data, src1, "src1", true, 1)) {
if (!rga_check_channel(job, data, src1, "src1", true, false, 1)) {
if (DEBUGGER_EN(MSG))
rga_job_log(job, "%s(%#x), break on src1",
rga_get_core_name(scheduler->core),
@@ -426,7 +443,7 @@ int rga_job_assign(struct rga_job *job)
}
}
if (!rga_check_channel(job, data, dst, "dst", false, 2)) {
if (!rga_check_channel(job, data, dst, "dst", false, need_swap, 2)) {
if (DEBUGGER_EN(MSG))
rga_job_log(job, "%s(%#x), break on dst",
rga_get_core_name(scheduler->core),