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UPSTREAM: clk: rockchip: fix the incorrect pclk_edp div width for RK3399

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The range of the  pclk_edp_div_con is [13:8] and 6 bits, not 5.

Reported-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Tested-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 3e1531dbc3)

Change-Id: Ieffcad3f6d44c71d83b7ed00dd30a4bd45995bb2
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Xing Zheng
2017-01-18 12:20:56 +08:00
committed by Tao Huang
parent dee1e02869
commit 913ae6b724
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/rockchip/clk-rk3399.c
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@@ -1218,7 +1218,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
RK3399_CLKGATE_CON(11), 8, GFLAGS),
COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 5, DFLAGS,
RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 6, DFLAGS,
RK3399_CLKGATE_CON(11), 11, GFLAGS),
GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(32), 12, GFLAGS),