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drm/rockchip: px30 vop: set win2 zorder to 2

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Change-Id: Id0d510ce4f247d14646d51bba4dfa94383ff8e29
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
This commit is contained in:
Sandy Huang
2018-02-12 15:05:02 +08:00
parent ddcb4f03b5
commit 91b8d990c0
3 changed files with 4 additions and 1 deletions
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1
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
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@@ -3111,6 +3111,7 @@ static void vop_cfg_update(struct drm_crtc *crtc,
VOP_CTRL_SET(vop, afbdc_en, s->afbdc_en);
VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
VOP_CTRL_SET(vop, win2_zpos, 2);
vop_post_config(crtc);
spin_unlock(&vop->reg_lock);

1
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View File

@@ -228,6 +228,7 @@ struct vop_ctrl {
struct vop_reg st2084oetf_post_conv_en;
struct vop_reg win_csc_mode_sel;
struct vop_reg win2_zpos;
struct vop_reg reg_done_frm;
struct vop_reg cfg_done;
};

3
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
View File

@@ -1416,7 +1416,7 @@ static const struct vop_ctrl px30_ctrl_data = {
.dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0),
.global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13),
.auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0),
.dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xff, 22),
.dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 22),
.overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4),
.core_dclk_div = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 13),
.dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14),
@@ -1476,6 +1476,7 @@ static const struct vop_ctrl px30_ctrl_data = {
.cabc_stage_down = VOP_REG(PX30_CABC_CTRL2, 0xff, 0),
.cabc_global_dn = VOP_REG(PX30_CABC_CTRL3, 0xff, 0),
.cabc_global_dn_limit_en = VOP_REG(PX30_CABC_CTRL3, 0x1, 8),
.win2_zpos = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x3, 26),
};
static const struct vop_win_phy px30_win23_data = {