misc: rk628: hdmitx: pll configured within the range of values specified by spec

The specification states that the pre-dividing ratio ranges from
1≤N≤15 and the feedback dividing ratio ranges from 16≤M≤512, and
lower values have a eliminating effect on external reference clock
jitter.

The following example is given in specification:
Bandwidth       Frequency(MHz)  N/M
1.41MHz         148.5           2/20
458KHz          148.5           3/30
322.89KHz       148.5           6/60
229KHz          148.5           12/120

Here the configuration is configured according to the minimum
value in the sample

Type: Fix
Redmine ID: N/A
Associated modifications: N/A
Test: N/A

Signed-off-by: Zhibin Huang <zhibin.huang@rock-chips.com>
Change-Id: I73e9cc5d70816e5409a48866430ed3762821909b
This commit is contained in:
Zhibin Huang
2024-08-22 07:56:12 +08:00
parent f03f3720bb
commit 92364ef8ee

View File

@@ -511,9 +511,9 @@ static int rk628_hdmi_config_video_timing(struct rk628_hdmi *hdmi,
value = mode->vsync_end - mode->vsync_start;
hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDURATION, value & 0xFF);
hdmi_writeb(hdmi, HDMI_PHY_PRE_DIV_RATIO, 0x1e);
hdmi_writeb(hdmi, PHY_FEEDBACK_DIV_RATIO_LOW, 0x2c);
hdmi_writeb(hdmi, PHY_FEEDBACK_DIV_RATIO_HIGH, 0x01);
hdmi_writeb(hdmi, HDMI_PHY_PRE_DIV_RATIO, 0x02);
hdmi_writeb(hdmi, PHY_FEEDBACK_DIV_RATIO_LOW, 0x14);
hdmi_writeb(hdmi, PHY_FEEDBACK_DIV_RATIO_HIGH, 0x00);
return 0;
}