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Revert "drm/rockchip: vop2: Disable aclk of video port when it unused"

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This reverts commit e5cb1f01cd.

This function is not stable.

u-boot should also revert this commit:
0b728e80d451 ("drm/rockchip: vop2: disabled aclk of video port when unused")

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I8f3b1180c29a670433a12993f18b33716bef288f
This commit is contained in:
Andy Yan
2022-03-14 17:34:25 +08:00
committed by Tao Huang
parent 252b7b1c4b
commit 925acfb272
3 changed files with 2 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View File

@@ -701,7 +701,6 @@ struct vop2_video_port_regs {
struct vop_reg dclk_core_div;
struct vop_reg dclk_out_div;
struct vop_reg dclk_src_sel;
struct vop_reg aclk_en;
struct vop_reg splice_en;

11
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -3286,11 +3286,9 @@ static void vop2_initial(struct drm_crtc *crtc)
VOP_CTRL_SET(vop2, cfg_done_en, 1);
/*
* Disable auto gating, this is a workaround to
* avoid display image shift when a window enabled
* on rk3566/rk3568.
* avoid display image shift when a window enabled.
*/
if (vop2->version == VOP_VERSION_RK3568)
VOP_CTRL_SET(vop2, auto_gating_en, 0);
VOP_CTRL_SET(vop2, auto_gating_en, 0);
/*
* Register OVERLAY_LAYER_SEL and OVERLAY_PORT_SEL should take effect immediately,
* than windows configuration(CLUSTER/ESMART/SMART) can take effect according the
@@ -3308,7 +3306,6 @@ static void vop2_initial(struct drm_crtc *crtc)
vop2->is_enabled = true;
}
VOP_MODULE_SET(vop2, vp, aclk_en, 1);
vop2_debug_irq_enable(crtc);
vop2->enable_count++;
@@ -3376,7 +3373,6 @@ static void vop2_power_domain_off_by_disabled_vp(struct vop2_power_domain *pd)
DRM_DEV_ERROR(vop2->dev, "failed to enable dclk for video port%d - %d\n",
vp->id, ret);
crtc = &vp->rockchip_crtc.crtc;
VOP_MODULE_SET(vop2, vp, aclk_en, 1);
VOP_MODULE_SET(vop2, vp, standby, 0);
vop2_power_domain_off(pd);
vop2_cfg_done(crtc);
@@ -3390,7 +3386,6 @@ static void vop2_power_domain_off_by_disabled_vp(struct vop2_power_domain *pd)
DRM_DEV_INFO(vop2->dev, "wait for vp%d dsp_hold timeout\n", vp->id);
vop2_dsp_hold_valid_irq_disable(crtc);
VOP_MODULE_SET(vop2, vp, aclk_en, 0);
clk_disable_unprepare(vp->dclk);
}
}
@@ -3806,8 +3801,6 @@ static void vop2_crtc_atomic_disable(struct drm_crtc *crtc,
vop2_dsp_hold_valid_irq_disable(crtc);
VOP_MODULE_SET(vop2, vp, aclk_en, 0);
vop2_disable(crtc);
vcstate->splice_mode = false;

4
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
View File

@@ -895,7 +895,6 @@ static const struct vop2_video_port_regs rk3588_vop_vp0_regs = {
.splice_en = VOP_REG(RK3568_LUT_PORT_SEL, 0x1, 16),
.dclk_core_div = VOP_REG(RK3568_VP0_CLK_CTRL, 0x3, 0),
.dclk_out_div = VOP_REG(RK3568_VP0_CLK_CTRL, 0x3, 2),
.aclk_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 25),
.pre_scan_htiming = VOP_REG(RK3568_VP0_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
.bg_dly = VOP_REG(RK3568_VP0_BG_MIX_CTRL, 0xff, 24),
.hpost_st_end = VOP_REG(RK3568_VP0_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
@@ -987,7 +986,6 @@ static const struct vop2_video_port_regs rk3588_vop_vp1_regs = {
.standby = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31),
.dclk_core_div = VOP_REG(RK3568_VP1_CLK_CTRL, 0x3, 0),
.dclk_out_div = VOP_REG(RK3568_VP1_CLK_CTRL, 0x3, 2),
.aclk_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 26),
.pre_scan_htiming = VOP_REG(RK3568_VP1_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
.bg_dly = VOP_REG(RK3568_VP1_BG_MIX_CTRL, 0xff, 24),
.hpost_st_end = VOP_REG(RK3568_VP1_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
@@ -1075,7 +1073,6 @@ static const struct vop2_video_port_regs rk3588_vop_vp2_regs = {
.dclk_src_sel = VOP_REG(RK3568_LUT_PORT_SEL, 0x1, 31),
.dclk_core_div = VOP_REG(RK3568_VP2_CLK_CTRL, 0x3, 0),
.dclk_out_div = VOP_REG(RK3568_VP2_CLK_CTRL, 0x3, 2),
.aclk_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 27),
.pre_scan_htiming = VOP_REG(RK3568_VP2_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
.bg_dly = VOP_REG(RK3568_VP2_BG_MIX_CTRL, 0xff, 24),
.hpost_st_end = VOP_REG(RK3568_VP2_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
@@ -1133,7 +1130,6 @@ static const struct vop2_video_port_regs rk3588_vop_vp3_regs = {
.dclk_src_sel = VOP_REG(RK3568_LUT_PORT_SEL, 0x1, 30),
.dclk_core_div = VOP_REG(RK3568_VP3_CLK_CTRL, 0x3, 0),
.dclk_out_div = VOP_REG(RK3568_VP3_CLK_CTRL, 0x3, 2),
.aclk_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 28),
.pre_scan_htiming = VOP_REG(RK3588_VP3_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
.bg_dly = VOP_REG(RK3588_VP3_BG_MIX_CTRL, 0xff, 24),
.hpost_st_end = VOP_REG(RK3588_VP3_POST_DSP_HACT_INFO, 0x1fff1fff, 0),