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drm: rockchip: rk628: Add rk628 combrx-phy driver
Change-Id: I0fbcca09e05c9876ae7e87000d1fa5b72a061077 Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
This commit is contained in:
Algea Cao
@@ -3,7 +3,8 @@
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# Makefile for the Rockchip RK628 display bridge driver.
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#
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obj-$(CONFIG_DRM_ROCKCHIP_RK628) += rk628_combtxphy.o \
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obj-$(CONFIG_DRM_ROCKCHIP_RK628) += rk628_combrxphy.o \
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rk628_combtxphy.o \
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rk628_dsi.o \
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rk628_gvi.o \
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rk628_lvds.o \
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665
drivers/gpu/drm/rockchip/rk628/rk628_combrxphy.c
Normal file
665
drivers/gpu/drm/rockchip/rk628/rk628_combrxphy.c
Normal file
@@ -0,0 +1,665 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
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*
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* Author: Algea Cao <algea.cao@rock-chips.com>
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*/
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/phy/phy.h>
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#include <linux/mfd/rk628.h>
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#define REG(x) ((x) + 0x10000)
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#define COMBRXPHY_MAX_REGISTER REG(0x6780)
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struct rk628_combrxphy {
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struct device *dev;
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struct rk628 *parent;
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struct regmap *regmap;
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struct clk *pclk;
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struct reset_control *rstc;
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enum phy_mode mode;
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};
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#define MAX_ROUND 12
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#define MAX_DATA_NUM 16
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#define MAX_CHANNEL 3
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static void rk628_combrxphy_set_data_of_round(struct rk628_combrxphy
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*combrxphy, u32 *data,
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u32 *data_in)
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{
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data_in[0] = data[0];
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data_in[1] = data[7];
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data_in[2] = data[13];
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data_in[3] = data[14];
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data_in[4] = data[15];
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data_in[5] = data[1];
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data_in[6] = data[2];
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data_in[7] = data[3];
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data_in[8] = data[4];
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data_in[9] = data[5];
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data_in[10] = data[6];
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data_in[11] = data[8];
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data_in[12] = data[9];
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data_in[13] = data[10];
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data_in[14] = data[11];
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data_in[15] = data[12];
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}
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static void
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rk628_combrxphy_max_zero_of_round(struct rk628_combrxphy *combrxphy,
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u32 *data_in, u32 *max_zero, u32 *max_val,
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int n, int ch)
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{
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int i;
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int cnt = 0;
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int max_cnt = 0;
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u32 max_v = 0;
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dev_dbg(combrxphy->dev, "%s channel:%d, round:%d ==============\n",
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__func__, ch, n);
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for (i = 0; i < MAX_DATA_NUM; i++) {
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dev_dbg(combrxphy->dev, "0x%02x ", data_in[i]);
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if ((i + 1) % MAX_ROUND == 0)
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dev_dbg(combrxphy->dev, "\n");
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}
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for (i = 0; i < MAX_DATA_NUM; i++) {
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if (max_v < data_in[i])
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max_v = data_in[i];
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}
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for (i = 0; i < MAX_DATA_NUM; i++) {
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if (data_in[i] == 0)
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cnt = cnt + 200;
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else if (data_in[i] > 0 && data_in[i] < 100)
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cnt = cnt + 100 - data_in[i];
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}
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max_cnt = cnt >= 3200 ? 0 : cnt;
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max_zero[n] = max_cnt;
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max_val[n] = max_v;
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dev_dbg(combrxphy->dev, "channel:%d,round:%d,max_zero_cnt:%d,max_val:%#x",
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ch, n, max_zero[n], max_val[n]);
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}
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static int
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rk628_combrxphy_chose_round_for_ch(struct rk628_combrxphy *combrxphy,
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u32 *rd_max_zero,
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u32 *rd_max_val, int ch,
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int min_round, int max_round)
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{
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int i, rd = 0;
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u32 max = 0;
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u32 max_v = 0;
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dev_dbg(combrxphy->dev, "%s channel:%d=============\n", __func__, ch);
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for (i = min_round; i < max_round; i++) {
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dev_dbg(combrxphy->dev, "0x%02x ", rd_max_zero[i]);
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if ((i + 1) % max_round == 0)
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dev_dbg(combrxphy->dev, "\n");
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}
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dev_dbg(combrxphy->dev, "\n");
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for (i = min_round; i < max_round; i++) {
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dev_dbg(combrxphy->dev, "0x%02x ", rd_max_val[i]);
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if ((i + 1) % max_round == 0)
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dev_dbg(combrxphy->dev, "\n");
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}
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for (i = min_round; i < max_round; i++) {
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if (rd_max_zero[i] > max) {
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max = rd_max_zero[i];
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max_v = rd_max_val[i];
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rd = i;
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} else if (rd_max_zero[i] == max && rd_max_val[i] > max_v) {
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max = rd_max_zero[i];
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max_v = rd_max_val[i];
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rd = i;
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}
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}
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dev_dbg(combrxphy->dev, "%s channel:%d, rd:%d\n", __func__, ch, rd);
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return rd;
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}
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static void rk628_combrxphy_get_data_of_round(struct rk628_combrxphy
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*combrxphy, u32 *data)
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{
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u32 i;
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for (i = 0; i < MAX_DATA_NUM; i++)
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regmap_read(combrxphy->regmap, REG(0x6740 + i * 4), &data[i]);
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}
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static void
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rk628_combrxphy_set_dc_gain(struct rk628_combrxphy *combrxphy,
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u32 x, u32 y, u32 z)
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{
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u32 val;
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u32 dc_gain_ch0, dc_gain_ch1, dc_gain_ch2;
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dev_dbg(combrxphy->dev, "channel dc gain x:%d, y:%d, z:%d", x, y, z);
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dc_gain_ch0 = x & 0xf;
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dc_gain_ch1 = y & 0xf;
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dc_gain_ch2 = z & 0xf;
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regmap_read(combrxphy->regmap, REG(0x661c), &val);
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val = (val & 0xff0f0f0f) | (dc_gain_ch0 << 20) | (dc_gain_ch1 << 12) |
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(dc_gain_ch2 << 4);
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regmap_write(combrxphy->regmap, REG(0x661c), val);
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}
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static void rk628_combrxphy_set_sample_edge_round(struct rk628_combrxphy
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*combrxphy, u32 x, u32 y, u32 z)
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{
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u32 val;
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u32 lsb_ch0;
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u32 lsb_ch1;
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u32 lsb_ch2;
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dev_dbg(combrxphy->dev, "channel sample edge x:%d, y:%d, z:%d",
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x, y, z);
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lsb_ch0 = (x & 0xf);
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lsb_ch1 = (y & 0xf);
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lsb_ch2 = (z & 0xf);
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regmap_read(combrxphy->regmap, REG(0x6618), &val);
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val = (val & 0xff00f0ff) | (lsb_ch1 << 20) | (lsb_ch0 << 16) |
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(lsb_ch2 << 8);
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regmap_write(combrxphy->regmap, REG(0x6618), val);
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}
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static void rk628_combrxphy_start_sample_edge(struct rk628_combrxphy *combrxphy)
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{
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u32 val;
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regmap_read(combrxphy->regmap, REG(0x66f0), &val);
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val &= 0xfffff1ff;
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regmap_write(combrxphy->regmap, REG(0x66f0), val);
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regmap_read(combrxphy->regmap, REG(0x66f0), &val);
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val = (val & 0xfffff1ff) | (0x7 << 9);
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regmap_write(combrxphy->regmap, REG(0x66f0), val);
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}
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static void
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rk628_combrxphy_set_sample_edge_mode(struct rk628_combrxphy *combrxphy,
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int ch)
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{
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u32 val;
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dev_dbg(combrxphy->dev, "%s in!", __func__);
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regmap_read(combrxphy->regmap, REG(0x6634), &val);
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dev_dbg(combrxphy->dev, "%s read val:%#x!", __func__, val);
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val = val & (~(0xf << ((ch + 1) * 4)));
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dev_dbg(combrxphy->dev, "%s write val:%#x!", __func__, val);
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regmap_write(combrxphy->regmap, REG(0x6634), val);
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dev_dbg(combrxphy->dev, "%s out!", __func__);
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}
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static void rk628_combrxphy_select_channel(struct rk628_combrxphy *combrxphy,
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int ch)
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{
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u32 val;
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regmap_read(combrxphy->regmap, REG(0x6700), &val);
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val = (val & 0xfffffffc) | (ch & 0x3);
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regmap_write(combrxphy->regmap, REG(0x6700), val);
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}
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static void rk628_combrxphy_cfg_6730(struct rk628_combrxphy *combrxphy)
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{
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u32 val;
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regmap_read(combrxphy->regmap, REG(0x6730), &val);
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val = (val & 0xffff0000) | 0x1;
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regmap_write(combrxphy->regmap, REG(0x6730), val);
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}
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static void
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rk628_combrxphy_sample_edge_procedure(struct rk628_combrxphy *combrxphy,
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int f, int min_round,
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int max_round)
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{
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int n, ch;
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u32 data[MAX_DATA_NUM];
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u32 data_in[MAX_DATA_NUM];
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u32 round_max_zero[MAX_CHANNEL][max_round];
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u32 round_max_value[MAX_CHANNEL][max_round];
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u32 ch_round[MAX_CHANNEL];
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u32 edge, dc_gain;
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dev_dbg(combrxphy->dev, "%s in!", __func__);
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/* Step1: set sample edge mode for channel 0~2 */
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for (ch = 0; ch < MAX_CHANNEL; ch++)
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rk628_combrxphy_set_sample_edge_mode(combrxphy, ch);
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dev_dbg(combrxphy->dev, "step1 set sample edge mode ok!");
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/* step2: once per round */
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for (ch = 0; ch < MAX_CHANNEL; ch++) {
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rk628_combrxphy_select_channel(combrxphy, ch);
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rk628_combrxphy_cfg_6730(combrxphy);
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}
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dev_dbg(combrxphy->dev, "step2 once per round ok!");
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/*
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* step3:config sample edge until the end of one frame
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* (for example 1080p:2200*1125=32’h25c3f8)
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*/
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switch (f) {
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case 27000:
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edge = 858 * 525;
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dc_gain = 0;
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break;
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case 64000:
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edge = 1317 * 810;
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dc_gain = 0;
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break;
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case 74250:
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edge = 1650 * 750;
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dc_gain = 0;
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break;
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case 148500:
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edge = 2200 * 1125;
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dc_gain = 1;
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break;
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case 297000:
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dc_gain = 3;
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edge = 4400 * 2250;
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break;
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case 594000:
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dc_gain = 0xf;
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edge = 4400 * 2250;
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break;
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default:
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edge = 2200 * 1125;
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dc_gain = 1;
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break;
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}
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dev_dbg(combrxphy->dev, "===>>> f:%d, edge:%#x", f, edge);
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for (ch = 0; ch < MAX_CHANNEL; ch++) {
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rk628_combrxphy_select_channel(combrxphy, ch);
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regmap_write(combrxphy->regmap, REG(0x6708), edge);
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}
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dev_dbg(combrxphy->dev, "step3 cfg sample edge ok!");
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rk628_combrxphy_set_dc_gain(combrxphy, dc_gain, dc_gain, dc_gain);
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for (n = min_round; n < max_round; n++) {
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/* step4:set sample edge round value n,n=0(n=0~31) */
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rk628_combrxphy_set_sample_edge_round(combrxphy, n, n, n);
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dev_dbg(combrxphy->dev, "step4 ok!");
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/* step5:start sample edge */
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rk628_combrxphy_start_sample_edge(combrxphy);
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dev_dbg(combrxphy->dev, "step5 ok!");
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/* step6:waiting more than one frame time */
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usleep_range(40*1000, 41*1000);
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for (ch = 0; ch < MAX_CHANNEL; ch++) {
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/* step7:get data of round n */
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rk628_combrxphy_select_channel(combrxphy, ch);
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dev_dbg(combrxphy->dev, "step7 set ch ok!");
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rk628_combrxphy_get_data_of_round(combrxphy, data);
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dev_dbg(combrxphy->dev, "step7 get data ok!");
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rk628_combrxphy_set_data_of_round(combrxphy, data,
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data_in);
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dev_dbg(combrxphy->dev, "step7 set data ok!");
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rk628_combrxphy_max_zero_of_round(combrxphy, data_in,
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round_max_zero[ch],
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round_max_value[ch],
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n, ch);
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}
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}
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for (ch = 0; ch < MAX_CHANNEL; ch++)
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ch_round[ch] =
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rk628_combrxphy_chose_round_for_ch(combrxphy,
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round_max_zero[ch],
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round_max_value[ch],
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ch, min_round,
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max_round);
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/*
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* step8:after finish round 31, get the max constant value and
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* corresponding value n.
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* write result to sample edge round value.
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*/
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rk628_combrxphy_set_sample_edge_round(combrxphy, ch_round[0],
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ch_round[1], ch_round[2]);
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/* do step5, step6 again */
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dev_dbg(combrxphy->dev, "do step5 step6 again!");
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rk628_combrxphy_start_sample_edge(combrxphy);
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usleep_range(40*1000, 41*1000);
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}
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static int rk628_combrxphy_set_hdmi_mode(struct rk628_combrxphy *combrxphy,
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int bus_width)
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{
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u32 val, data_a, data_b, f, val2 = 0;
|
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int i, ret, count;
|
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int pll_man, max_round, min_round;
|
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bool is_yuv420;
|
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|
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is_yuv420 = bus_width & BIT(30);
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|
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if (is_yuv420)
|
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f = (bus_width & 0xffffff) / 2;
|
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else
|
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f = bus_width & 0xffffff;
|
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|
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dev_dbg(combrxphy->dev, "f:%d\n", f);
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|
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regmap_read(combrxphy->regmap, REG(0x6630), &val);
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val &= ~BIT(23);
|
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val |= 0x18;
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regmap_write(combrxphy->regmap, REG(0x6630), val);
|
||||
|
||||
/* enable cal */
|
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regmap_read(combrxphy->regmap, REG(0x6610), &val);
|
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val |= 0x18000000;
|
||||
regmap_write(combrxphy->regmap, REG(0x6610), val);
|
||||
|
||||
usleep_range(10*1000, 11*1000);
|
||||
/* disable cal */
|
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val &= ~BIT(28);
|
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val |= BIT(27);
|
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regmap_write(combrxphy->regmap, REG(0x6610), val);
|
||||
|
||||
/* save cal val */
|
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regmap_read(combrxphy->regmap, REG(0x6614), &val);
|
||||
if (!(val & 0x3f00)) {
|
||||
dev_err(combrxphy->dev, "resistor error\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
val &= 0x3f00;
|
||||
val = val >> 8;
|
||||
val2 |= 0x40404040;
|
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val2 |= val << 24 | val << 16 | val << 8 | val;
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||||
|
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/* rtm inc */
|
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regmap_read(combrxphy->regmap, REG(0x6604), &val);
|
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val |= BIT(31);
|
||||
regmap_write(combrxphy->regmap, REG(0x6604), val);
|
||||
|
||||
regmap_write(combrxphy->regmap, REG(0x6620), val2);
|
||||
|
||||
/* rtm en bypass */
|
||||
regmap_read(combrxphy->regmap, REG(0x6600), &val);
|
||||
val |= BIT(7);
|
||||
regmap_write(combrxphy->regmap, REG(0x6600), val);
|
||||
|
||||
/* rtm prot en bypass */
|
||||
regmap_read(combrxphy->regmap, REG(0x6610), &val);
|
||||
val |= 0x80f000;
|
||||
regmap_write(combrxphy->regmap, REG(0x6610), val);
|
||||
|
||||
regmap_read(combrxphy->regmap, REG(0x661c), &val);
|
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val |= 0x81000000;
|
||||
regmap_write(combrxphy->regmap, REG(0x661c), val);
|
||||
|
||||
/* enable pll */
|
||||
regmap_read(combrxphy->regmap, REG(0x6630), &val);
|
||||
val &= ~BIT(4);
|
||||
val |= BIT(3);
|
||||
regmap_write(combrxphy->regmap, REG(0x6630), val);
|
||||
|
||||
/* equ en */
|
||||
regmap_read(combrxphy->regmap, REG(0x6618), &val);
|
||||
val |= BIT(4);
|
||||
regmap_write(combrxphy->regmap, REG(0x6618), val);
|
||||
|
||||
regmap_read(combrxphy->regmap, REG(0x6614), &val);
|
||||
val |= 0x10900000;
|
||||
regmap_write(combrxphy->regmap, REG(0x6614), val);
|
||||
|
||||
regmap_read(combrxphy->regmap, REG(0x6610), &val);
|
||||
val |= 0xf00;
|
||||
regmap_write(combrxphy->regmap, REG(0x6610), val);
|
||||
|
||||
regmap_read(combrxphy->regmap, REG(0x6630), &val);
|
||||
val |= 0x870000;
|
||||
regmap_write(combrxphy->regmap, REG(0x6630), val);
|
||||
|
||||
udelay(10);
|
||||
|
||||
/* get cdr_mode,make sure cdr_mode != 5’h1f */
|
||||
regmap_read(combrxphy->regmap, REG(0x6654), &val);
|
||||
if ((val & 0x1f0000) == 0x1f0000)
|
||||
dev_err(combrxphy->dev, "error,clock error!");
|
||||
|
||||
/* manually configure PLL */
|
||||
if (f <= 340000) {
|
||||
regmap_write(combrxphy->regmap, REG(0x662c), 0x01000500);
|
||||
if (is_yuv420)
|
||||
regmap_write(combrxphy->regmap, REG(0x66a8),
|
||||
0x0000c000);
|
||||
else
|
||||
regmap_write(combrxphy->regmap, REG(0x66a8),
|
||||
0x0000c600);
|
||||
} else {
|
||||
regmap_write(combrxphy->regmap, REG(0x662c), 0x01001400);
|
||||
regmap_write(combrxphy->regmap, REG(0x66a8), 0x0000c600);
|
||||
}
|
||||
|
||||
switch (f) {
|
||||
case 27000:
|
||||
case 64000:
|
||||
case 74250:
|
||||
max_round = 6;
|
||||
min_round = 0;
|
||||
pll_man = 0x7964c;
|
||||
break;
|
||||
case 148500:
|
||||
pll_man = 0x7a1c8;
|
||||
max_round = 6;
|
||||
min_round = 0;
|
||||
break;
|
||||
case 297000:
|
||||
pll_man = 0x7a108;
|
||||
max_round = 8;
|
||||
min_round = 2;
|
||||
break;
|
||||
case 594000:
|
||||
pll_man = 0x7f0c8;
|
||||
max_round = 4;
|
||||
min_round = 10;
|
||||
break;
|
||||
default:
|
||||
pll_man = 0x7964c;
|
||||
max_round = 1;
|
||||
min_round = 12;
|
||||
break;
|
||||
}
|
||||
|
||||
pll_man |= BIT(23);
|
||||
regmap_write(combrxphy->regmap, REG(0x6630), pll_man);
|
||||
|
||||
/* EQ and SAMPLE cfg */
|
||||
rk628_combrxphy_sample_edge_procedure(combrxphy, f, min_round,
|
||||
max_round);
|
||||
|
||||
/* Deassert fifo reset,enable fifo write and read */
|
||||
regmap_write(combrxphy->regmap, REG(0x66a0), 0x00000003);
|
||||
regmap_write(combrxphy->regmap, REG(0x66b0), 0x00080060);
|
||||
regmap_write(combrxphy->regmap, REG(0x66a0), 0x00000083);
|
||||
regmap_write(combrxphy->regmap, REG(0x66b0), 0x00380060);
|
||||
regmap_update_bits(combrxphy->regmap, REG(0x66ac), GENMASK(31, 24),
|
||||
UPDATE(0x22, 31, 24));
|
||||
usleep_range(10*1000, 11*1000);
|
||||
|
||||
/* check all 3 data channels alignment */
|
||||
count = 0;
|
||||
for (i = 0; i < 100; i++) {
|
||||
udelay(100);
|
||||
regmap_read(combrxphy->regmap, REG(0x66b4), &data_a);
|
||||
regmap_read(combrxphy->regmap, REG(0x66b8), &data_b);
|
||||
/* ch0 ch1 ch2 lock */
|
||||
if (((data_a & 0x00ff00ff) == 0x00ff00ff) &&
|
||||
((data_b & 0xff) == 0xff))
|
||||
count++;
|
||||
}
|
||||
|
||||
if (count >= 100) {
|
||||
dev_info(combrxphy->dev, "channel alignment done");
|
||||
ret = 0;
|
||||
} else if (count > 0) {
|
||||
dev_err(combrxphy->dev, "not stable, count:%d of 100", count);
|
||||
ret = -EINVAL;
|
||||
} else {
|
||||
dev_err(combrxphy->dev, "channel alignment failed!");
|
||||
ret = -EINVAL;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rk628_combrxphy_power_on(struct phy *phy)
|
||||
{
|
||||
struct rk628_combrxphy *combrxphy = phy_get_drvdata(phy);
|
||||
int f = phy_get_bus_width(phy);
|
||||
|
||||
clk_prepare_enable(combrxphy->pclk);
|
||||
reset_control_deassert(combrxphy->rstc);
|
||||
|
||||
return rk628_combrxphy_set_hdmi_mode(combrxphy, f);
|
||||
}
|
||||
|
||||
static int rk628_combrxphy_power_off(struct phy *phy)
|
||||
{
|
||||
struct rk628_combrxphy *combrxphy = phy_get_drvdata(phy);
|
||||
|
||||
reset_control_assert(combrxphy->rstc);
|
||||
clk_disable_unprepare(combrxphy->pclk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk628_combrxphy_set_mode(struct phy *phy, enum phy_mode mode)
|
||||
{
|
||||
struct rk628_combrxphy *combrxphy = phy_get_drvdata(phy);
|
||||
|
||||
combrxphy->mode = mode;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct phy_ops rk628_combrxphy_ops = {
|
||||
.set_mode = rk628_combrxphy_set_mode,
|
||||
.power_on = rk628_combrxphy_power_on,
|
||||
.power_off = rk628_combrxphy_power_off,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static const struct regmap_range rk628_combrxphy_readable_ranges[] = {
|
||||
regmap_reg_range(REG(0x6600), REG(0x665b)),
|
||||
regmap_reg_range(REG(0x66a0), REG(0x66db)),
|
||||
regmap_reg_range(REG(0x66f0), REG(0x66ff)),
|
||||
regmap_reg_range(REG(0x6700), REG(0x6790)),
|
||||
};
|
||||
|
||||
static const struct regmap_access_table rk628_combrxphy_readable_table = {
|
||||
.yes_ranges = rk628_combrxphy_readable_ranges,
|
||||
.n_yes_ranges = ARRAY_SIZE(rk628_combrxphy_readable_ranges),
|
||||
};
|
||||
|
||||
static const struct regmap_config rk628_combrxphy_regmap_cfg = {
|
||||
.name = "combrxphy",
|
||||
.reg_bits = 32,
|
||||
.val_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.max_register = COMBRXPHY_MAX_REGISTER,
|
||||
.reg_format_endian = REGMAP_ENDIAN_LITTLE,
|
||||
.val_format_endian = REGMAP_ENDIAN_LITTLE,
|
||||
.rd_table = &rk628_combrxphy_readable_table,
|
||||
};
|
||||
|
||||
static int rk628_combrxphy_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
|
||||
struct device *dev = &pdev->dev;
|
||||
struct rk628_combrxphy *combrxphy;
|
||||
struct phy_provider *phy_provider;
|
||||
struct phy *phy;
|
||||
int ret;
|
||||
|
||||
if (!of_device_is_available(dev->of_node))
|
||||
return -ENODEV;
|
||||
|
||||
combrxphy = devm_kzalloc(dev, sizeof(*combrxphy), GFP_KERNEL);
|
||||
if (!combrxphy)
|
||||
return -ENOMEM;
|
||||
|
||||
combrxphy->dev = dev;
|
||||
combrxphy->parent = rk628;
|
||||
platform_set_drvdata(pdev, combrxphy);
|
||||
|
||||
combrxphy->pclk = devm_clk_get(dev, "pclk");
|
||||
if (IS_ERR(combrxphy->pclk)) {
|
||||
ret = PTR_ERR(combrxphy->pclk);
|
||||
dev_err(dev, "failed to get pclk: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
combrxphy->rstc = of_reset_control_get(dev->of_node, NULL);
|
||||
if (IS_ERR(combrxphy->rstc)) {
|
||||
ret = PTR_ERR(combrxphy->rstc);
|
||||
dev_err(dev, "failed to get reset control: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
combrxphy->regmap = devm_regmap_init_i2c(rk628->client,
|
||||
&rk628_combrxphy_regmap_cfg);
|
||||
if (IS_ERR(combrxphy->regmap)) {
|
||||
ret = PTR_ERR(combrxphy->regmap);
|
||||
dev_err(dev, "failed to allocate host register map: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
phy = devm_phy_create(dev, NULL, &rk628_combrxphy_ops);
|
||||
if (IS_ERR(phy)) {
|
||||
ret = PTR_ERR(phy);
|
||||
dev_err(dev, "failed to create phy: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
phy_set_drvdata(phy, combrxphy);
|
||||
|
||||
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
||||
if (IS_ERR(phy_provider)) {
|
||||
ret = PTR_ERR(phy_provider);
|
||||
dev_err(dev, "failed to register phy provider: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id rk628_combrxphy_of_match[] = {
|
||||
{ .compatible = "rockchip,rk628-combrxphy", },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rk628_combrxphy_of_match);
|
||||
|
||||
static struct platform_driver rk628_combrxphy_driver = {
|
||||
.driver = {
|
||||
.name = "rk628-combrxphy",
|
||||
.of_match_table = of_match_ptr(rk628_combrxphy_of_match),
|
||||
},
|
||||
.probe = rk628_combrxphy_probe,
|
||||
};
|
||||
module_platform_driver(rk628_combrxphy_driver);
|
||||
|
||||
MODULE_AUTHOR("Algea Cao <algea.cao@rock-chips.com>");
|
||||
MODULE_DESCRIPTION("Rockchip RK628 HDMI Combo RX PHY driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Reference in New Issue
Block a user