hdmitx: hdmitx bringup for sm1 [1/1]

PD#SWPL-5408 Problem: hdmitx bringup for sm1 Solution: hdmitx bringup for sm1, add chip id Verify: sm1 ptm Change-Id: I804dec4b743c660b180b7061d110ab76b9ec0468 Signed-off-by: Yi Zhou <yi.zhou@amlogic.com>
2026-06-08 03:40:35 +09:00 · 2019-03-04 18:57:46 +08:00
parent f0d2cd13c6
commit 92eadbe3eb
7 changed files with 33 additions and 8 deletions
--- a/arch/arm/boot/dts/amlogic/mesonsm1.dtsi
+++ b/arch/arm/boot/dts/amlogic/mesonsm1.dtsi
@@ -1085,11 +1085,11 @@
 		/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
 		interrupts = <0 57 1>;
 		interrupt-names = "hdmitx_hpd";
-		/* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
-		 * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
-		 * 10:G12A
+		/* 0:M8B   1:GXBB 2:GXTVBB 3:GXL  4:GXM
+		 * 5:TXL   6:TXLX 7:AXG    8:GXLX 9:TXHD
+		 * 10:G12A 11:G12B 12:SM1
 		 */
-		ic_type = <10>;
+		ic_type = <12>;
 		vend_data: vend_data{ /* Should modified by Customer */
 			vendor_name = "Amlogic"; /* Max Chars: 8 */
 			/* standards.ieee.org/develop/regauth/oui/oui.txt */
--- a/arch/arm64/boot/dts/amlogic/mesonsm1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/mesonsm1.dtsi
@@ -1085,11 +1085,11 @@
 		/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
 		interrupts = <0 57 1>;
 		interrupt-names = "hdmitx_hpd";
-		/* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
-		 * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
-		 * 10:G12A
+		/* 0:M8B   1:GXBB 2:GXTVBB 3:GXL  4:GXM
+		 * 5:TXL   6:TXLX 7:AXG    8:GXLX 9:TXHD
+		 * 10:G12A 11:G12B 12:SM1
 		 */
-		ic_type = <10>;
+		ic_type = <12>;
 		vend_data: vend_data{ /* Should modified by Customer */
 			vendor_name = "Amlogic"; /* Max Chars: 8 */
 			/* standards.ieee.org/develop/regauth/oui/oui.txt */
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
@@ -117,6 +117,7 @@ int hdmitx_hpd_hw_op(enum hpd_op cmd)
 		return hdmitx_hpd_hw_op_txlx(cmd);
 	case MESON_CPU_ID_G12A:
 	case MESON_CPU_ID_G12B:
+	case MESON_CPU_ID_SM1:
 		return hdmitx_hpd_hw_op_g12a(cmd);
 	default:
 		break;
@@ -140,6 +141,7 @@ int read_hpd_gpio(void)
 	case MESON_CPU_ID_TXLX:
 	case MESON_CPU_ID_G12A:
 	case MESON_CPU_ID_G12B:
+	case MESON_CPU_ID_SM1:
 		return read_hpd_gpio_txlx();
 	default:
 		break;
@@ -163,6 +165,7 @@ int hdmitx_ddc_hw_op(enum ddc_op cmd)
 	case MESON_CPU_ID_TXLX:
 	case MESON_CPU_ID_G12A:
 	case MESON_CPU_ID_G12B:
+	case MESON_CPU_ID_SM1:
 		return hdmitx_ddc_hw_op_txlx(cmd);
 	default:
 		break;
@@ -391,6 +394,7 @@ static unsigned int hdmitx_get_format(void)
 	case MESON_CPU_ID_TXLX:
 	case MESON_CPU_ID_G12A:
 	case MESON_CPU_ID_G12B:
+	case MESON_CPU_ID_SM1:
 		ret = hdmitx_get_format_txlx();
 		break;
 	case MESON_CPU_ID_GXBB:
@@ -437,6 +441,7 @@ void hdmitx_sys_reset(void)
 	case MESON_CPU_ID_TXLX:
 	case MESON_CPU_ID_G12A:
 	case MESON_CPU_ID_G12B:
+	case MESON_CPU_ID_SM1:
 		hdmitx_sys_reset_txlx();
 		break;
 	case MESON_CPU_ID_GXBB:
@@ -1661,6 +1666,7 @@ static void set_phy_by_mode(unsigned int mode)
 	switch (hdev->chip_type) {
 	case MESON_CPU_ID_G12A:
 	case MESON_CPU_ID_G12B:
+	case MESON_CPU_ID_SM1:
 		switch (mode) {
 		case 1: /* 5.94/4.5/3.7Gbps */
 			hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37eb65c4);
@@ -2562,6 +2568,7 @@ static int hdmitx_cntl(struct hdmitx_dev *hdev, unsigned int cmd,
 			switch (hdev->chip_type) {
 			case MESON_CPU_ID_G12A:
 			case MESON_CPU_ID_G12B:
+			case MESON_CPU_ID_SM1:
 				hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 1, 29, 1);
 				udelay(50);
 				hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0, 28, 1);
@@ -4045,6 +4052,7 @@ static void hdmitx_debug(struct hdmitx_dev *hdev, const char *buf)
 		switch (hdev->chip_type) {
 		case MESON_CPU_ID_G12A:
 		case MESON_CPU_ID_G12B:
+		case MESON_CPU_ID_SM1:
 			for (i = 0; i < 4; i++) {
 				hd_write_reg(P_HHI_HDMI_PHY_CNTL1, 0x0390000f);
 				hd_write_reg(P_HHI_HDMI_PHY_CNTL1, 0x0390000e);
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_reg.h
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_reg.h
@@ -79,6 +79,10 @@ int hdmitx_hdcp_opr(unsigned int val);

 /* intr_maskn: MASK_N, one bit per interrupt source.
 *     1=Enable interrupt source; 0=Disable interrupt source. Default 0.
+ * [  8] hdcp_topology_err
+ * [  7] rxsense_fall
+ * [  6] rxsense_rise
+ * [  5] err_i2c_timeout
 * [  4] hdcp22_rndnum_err
 * [  3] nonce_rfrsh_rise
 * [  2] hpd_fall_intr
@@ -185,6 +189,7 @@ int hdmitx_hdcp_opr(unsigned int val);
 #define HDMITX_TOP_I2C_BUSY_CNT_STAT            (TOP_OFFSET_MASK + 0x029)
 #define HDMITX_TOP_HDCP22_BSOD                  (TOP_SEC_OFFSET_MASK + 0x02A)
 #define HDMITX_TOP_DDC_CNTL                     (TOP_OFFSET_MASK + 0x02B)
+#define HDMITX_TOP_DISABLE_NULL                     (TOP_OFFSET_MASK + 0x030)
 #define HDMITX_TOP_REVOCMEM_ADDR_S              (TOP_OFFSET_MASK + 0x2000 >> 2)
 #define HDMITX_TOP_REVOCMEM_ADDR_E              (TOP_OFFSET_MASK + 0x365E >> 2)

@@ -921,6 +926,8 @@ int hdmitx_hdcp_opr(unsigned int val);
 /* [  1] Rsvd for read-only ksv_mem_access */
 /* [  0] ksv_mem_request */
 #define HDMITX_DWC_A_KSVMEMCTRL                 (DWC_OFFSET_MASK + 0x5016)
+#define HDMITX_DWC_A_BSTATUS_HI                 (DWC_OFFSET_MASK + 0x5017)
+#define HDMITX_DWC_A_BSTATUS_LO                 (DWC_OFFSET_MASK + 0x5018)

 #define HDMITX_DWC_HDCP_BSTATUS_0               (TOP_OFFSET_MASK + 0x2000)
 #define HDMITX_DWC_HDCP_BSTATUS_1               (TOP_OFFSET_MASK + 0x2001)
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
@@ -165,6 +165,7 @@ void hdmitx_set_cts_hdcp22_clk(struct hdmitx_dev *hdev)
 	case MESON_CPU_ID_GXM:
 	case MESON_CPU_ID_G12A:
 	case MESON_CPU_ID_G12B:
+	case MESON_CPU_ID_SM1:
 	default:
 		hd_write_reg(P_HHI_HDCP22_CLK_CNTL, 0x01000100);
 	break;
@@ -441,6 +442,7 @@ static void set_hpll_clk_out(unsigned int clk)
 		break;
 	case MESON_CPU_ID_G12A:
 	case MESON_CPU_ID_G12B:
+	case MESON_CPU_ID_SM1:
 		set_g12a_hpll_clk_out(frac_rate, clk);
 		break;
 	default:
@@ -458,6 +460,7 @@ static void set_hpll_sspll(enum hdmi_vic vic)
 	switch (hdev->chip_type) {
 	case MESON_CPU_ID_G12A:
 	case MESON_CPU_ID_G12B:
+	case MESON_CPU_ID_SM1:
 		set_hpll_sspll_g12a(vic);
 		break;
 	case MESON_CPU_ID_GXBB:
@@ -503,6 +506,7 @@ static void set_hpll_od1(unsigned int div)
 		break;
 	case MESON_CPU_ID_G12A:
 	case MESON_CPU_ID_G12B:
+	case MESON_CPU_ID_SM1:
 		set_hpll_od1_g12a(div);
 		break;
 	default:
@@ -541,6 +545,7 @@ static void set_hpll_od2(unsigned int div)
 		break;
 	case MESON_CPU_ID_G12A:
 	case MESON_CPU_ID_G12B:
+	case MESON_CPU_ID_SM1:
 		set_hpll_od2_g12a(div);
 		break;
 	default:
@@ -579,6 +584,7 @@ static void set_hpll_od3(unsigned int div)
 		break;
 	case MESON_CPU_ID_G12A:
 	case MESON_CPU_ID_G12B:
+	case MESON_CPU_ID_SM1:
 		set_hpll_od3_g12a(div);
 		break;
 	default:
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/reg_ops.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/reg_ops.c
@@ -165,6 +165,7 @@ void init_reg_map(unsigned int type)
 	switch (type) {
 	case MESON_CPU_ID_G12A:
 	case MESON_CPU_ID_G12B:
+	case MESON_CPU_ID_SM1:
 		map = reg_maps_g12a;
 		for (i = 0; i < REG_IDX_END; i++) {
 			map[i].p = ioremap(map[i].phy_addr, map[i].size);
@@ -252,6 +253,7 @@ unsigned int hd_read_reg(unsigned int addr)
 	case MESON_CPU_ID_GXM:
 	case MESON_CPU_ID_G12A:
 	case MESON_CPU_ID_G12B:
+	case MESON_CPU_ID_SM1:
 	default:
 		val = readl(TO_PMAP_ADDR(addr));
 		break;
@@ -301,6 +303,7 @@ void hd_write_reg(unsigned int addr, unsigned int val)
 	case MESON_CPU_ID_GXM:
 	case MESON_CPU_ID_G12A:
 	case MESON_CPU_ID_G12B:
+	case MESON_CPU_ID_SM1:
 	default:
 		writel(val, TO_PMAP_ADDR(addr));
 		break;
--- a/include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h
+++ b/include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h
@@ -42,6 +42,7 @@
 #define MESON_CPU_ID_TXHD		9
 #define MESON_CPU_ID_G12A		10
 #define MESON_CPU_ID_G12B		11
+#define MESON_CPU_ID_SM1		12


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