shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-06 10:58:48 +09:00
Code Issues Packages Projects Releases Wiki Activity

drm/rockchip: vop2: add support vop state to triggle DMC

Browse Source 
VOP will triggle DMC at the following condition:

wb_en && wb_dma_finish && (vp lineflag || vp post full)

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I2ec972d74f7c8eab0088fcd96dc394e0d554020e
This commit is contained in:
Sandy Huang
2022-07-25 11:25:03 +08:00
committed by Tao Huang
parent b1aaf80222
commit 9310ffb31b
4 changed files with 34 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View File

@@ -922,6 +922,11 @@ struct vop2_video_port_regs {
struct vop_reg mcu_type;
struct vop_reg mcu_rw_bypass_port;
/* for DCF */
struct vop_reg line_flag_or_en;
struct vop_reg dsp_hold_or_en;
struct vop_reg almost_full_or_en;
/* CSC */
struct vop_reg acm_bypass_en;
struct vop_reg csc_en;
@@ -1206,6 +1211,9 @@ struct vop2_ctrl {
struct vop_reg wb_cfg_done;
struct vop_reg auto_gating_en;
struct vop_reg aclk_pre_auto_gating_en;
struct vop_reg dma_finish_mode;
struct vop_reg axi_dma_finish_and_en;
struct vop_reg wb_dma_finish_and_en;
struct vop_reg ovl_cfg_done_port;
struct vop_reg ovl_port_mux_cfg_done_imd;
struct vop_reg ovl_port_mux_cfg;

6
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -3263,6 +3263,7 @@ static void vop2_wb_commit(struct drm_crtc *crtc)
VOP_MODULE_SET(vop2, wb, r2y_en, r2y);
VOP_MODULE_SET(vop2, wb, enable, 1);
vop2_wb_irqs_enable(vop2);
VOP_CTRL_SET(vop2, wb_dma_finish_and_en, 1);
}
}
@@ -4236,6 +4237,8 @@ static void vop2_crtc_atomic_disable(struct drm_crtc *crtc,
vop2_lock(vop2);
DRM_DEV_INFO(vop2->dev, "Crtc atomic disable vp%d\n", vp->id);
VOP_MODULE_SET(vop2, vp, almost_full_or_en, 0);
VOP_MODULE_SET(vop2, vp, line_flag_or_en, 0);
drm_crtc_vblank_off(crtc);
if (vop2->dscs[vcstate->dsc_id].enabled &&
vop2->dscs[vcstate->dsc_id].attach_vp_id == vp->id &&
@@ -7625,6 +7628,8 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state
else
clk_set_rate(vp->dclk, adjusted_mode->crtc_clock * 1000);
VOP_MODULE_SET(vop2, vp, almost_full_or_en, 1);
VOP_MODULE_SET(vop2, vp, line_flag_or_en, 1);
if (vcstate->dsc_enable) {
if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
vop2_crtc_enable_dsc(crtc, old_state, 0);
@@ -9881,6 +9886,7 @@ static void vop2_wb_disable(struct vop2_video_port *vp)
struct vop2_wb *wb = &vop2->wb;
VOP_MODULE_SET(vop2, wb, enable, 0);
VOP_CTRL_SET(vop2, wb_dma_finish_and_en, 0);
vop2_wb_cfg_done(vp);
}

19
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
View File

@@ -1271,6 +1271,10 @@ static const struct vop2_video_port_regs rk3588_vop_vp0_regs = {
.cubic_lut_en = VOP_REG(RK3568_VP0_3D_LUT_CTRL, 0x1, 0),
.cubic_lut_update_en = VOP_REG(RK3568_VP0_3D_LUT_CTRL, 0x1, 2),
.cubic_lut_mst = VOP_REG(RK3568_VP0_3D_LUT_MST, 0xffffffff, 0),
.line_flag_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 20),
.dsp_hold_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 24),
.almost_full_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 28),
};
/*
@@ -1365,6 +1369,10 @@ static const struct vop2_video_port_regs rk3588_vop_vp1_regs = {
.cubic_lut_en = VOP_REG(RK3588_VP1_3D_LUT_CTRL, 0x1, 0),
.cubic_lut_update_en = VOP_REG(RK3588_VP1_3D_LUT_CTRL, 0x1, 2),
.cubic_lut_mst = VOP_REG(RK3588_VP1_3D_LUT_MST, 0xffffffff, 0),
.line_flag_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 21),
.dsp_hold_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 25),
.almost_full_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 29),
};
static const struct vop2_video_port_regs rk3588_vop_vp2_regs = {
@@ -1425,6 +1433,10 @@ static const struct vop2_video_port_regs rk3588_vop_vp2_regs = {
.cubic_lut_en = VOP_REG(RK3588_VP2_3D_LUT_CTRL, 0x1, 0),
.cubic_lut_update_en = VOP_REG(RK3588_VP2_3D_LUT_CTRL, 0x1, 2),
.cubic_lut_mst = VOP_REG(RK3588_VP2_3D_LUT_MST, 0xffffffff, 0),
.line_flag_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 22),
.dsp_hold_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 26),
.almost_full_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 30),
};
static const struct vop2_video_port_regs rk3588_vop_vp3_regs = {
@@ -1480,6 +1492,10 @@ static const struct vop2_video_port_regs rk3588_vop_vp3_regs = {
.edpi_te_en = VOP_REG(RK3588_VP3_DUAL_CHANNEL_CTRL, 0x1, 28),
.edpi_wms_hold_en = VOP_REG(RK3588_VP3_DUAL_CHANNEL_CTRL, 0x1, 30),
.edpi_wms_fs = VOP_REG(RK3588_VP3_DUAL_CHANNEL_CTRL, 0x1, 31),
.line_flag_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 23),
.dsp_hold_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 27),
.almost_full_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 31),
};
static const struct vop2_video_port_data rk3588_vop_video_ports[] = {
@@ -3260,6 +3276,9 @@ static const struct vop2_ctrl rk3588_vop_ctrl = {
.cfg_done_en = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 15),
.wb_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 14),
.auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 31),
.dma_finish_mode = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x3, 0),
.axi_dma_finish_and_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 2),
.wb_dma_finish_and_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 3),
.ovl_cfg_done_port = VOP_REG(RK3568_OVL_CTRL, 0x3, 30),
.ovl_port_mux_cfg_done_imd = VOP_REG(RK3568_OVL_CTRL, 0x1, 28),
.ovl_port_mux_cfg = VOP_REG(RK3568_OVL_PORT_SEL, 0xffff, 0),

1
drivers/gpu/drm/rockchip/rockchip_vop_reg.h
View File

@@ -1053,6 +1053,7 @@
#define RK3568_DSP_IF_CTRL 0x02c
#define RK3568_DSP_IF_POL 0x030
#define RK3568_SYS_PD_CTRL 0x034
#define RK3588_SYS_VAR_FREQ_CTRL 0x038
#define RK3568_WB_CTRL 0x40
#define RK3568_WB_XSCAL_FACTOR 0x44
#define RK3568_WB_YRGB_MST 0x48