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rk3066: force sdmmc & sdio even div
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@@ -294,6 +294,24 @@ static int clksel_set_rate_shift_2(struct clk *clk, unsigned long rate)
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}
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return -ENOENT;
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}
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//for div 1 2 4 2*n
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static int clksel_set_rate_even(struct clk *clk, unsigned long rate)
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{
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u32 div;
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for (div = 2; div < clk->div_max; div += 2) {
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u32 new_rate = clk->parent->rate / div;
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if (new_rate <= rate) {
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set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
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clk->rate = new_rate;
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pr_debug("%s for clock %s to rate %ld (even div = %d)\n",
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__func__, clk->name, rate, div);
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return 0;
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}
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}
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return -ENOENT;
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}
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static u32 clk_get_freediv(unsigned long rate_out, unsigned long rate ,u32 div_max)
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{
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u32 div;
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@@ -1649,7 +1667,7 @@ static struct clk clk_sdmmc = {
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.parent = &hclk_periph,
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.mode = gate_mode,
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.recalc = clksel_recalc_div,
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.set_rate = clksel_set_rate_freediv,
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.set_rate = clksel_set_rate_even,
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.gate_idx = CLK_GATE_MMC0,
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.clksel_con =CRU_CLKSELS_CON(11),
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CRU_DIV_SET(0x3f,0,64),
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@@ -1660,7 +1678,7 @@ static struct clk clk_sdio = {
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.parent = &hclk_periph,
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.mode = gate_mode,
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.recalc = clksel_recalc_div,
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.set_rate = clksel_set_rate_freediv,
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.set_rate = clksel_set_rate_even,
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.gate_idx = CLK_GATE_SDIO,
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.clksel_con =CRU_CLKSELS_CON(12),
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CRU_DIV_SET(0x3f,0,64),
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@@ -3372,6 +3390,8 @@ static void __init rk30_clock_common_init(unsigned long gpll_rate,unsigned long
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//clk_set_parent_nolock(&clk_gpu, &general_pll_clk);
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clk_set_rate_nolock(&clk_uart0, 49500000);
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clk_set_rate_nolock(&clk_sdmmc, 24750000);
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clk_set_rate_nolock(&clk_sdio, 24750000);
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}
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static struct clk def_ops_clk={
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