lcd: mipi_dsi: update clk_post timing for dphy [1/1]

PD#SWPL-2436

Problem:
sometime the dphy clk_post is not match spec

Solution:
update clk_post config

Verify:
w400

Change-Id: Ib6b585f833bf923e72109991509915f4ad35d316
Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>
This commit is contained in:
Evoke Zhang
2018-11-23 21:55:44 +08:00
committed by Jianxin Pan
parent 2c29197920
commit 93cc0f07ee

View File

@@ -497,7 +497,7 @@ static void dsi_phy_init(struct dsi_phy_s *dphy, unsigned char lane_num)
/* 0x05210f08);//0x03211c08 */
dsi_phy_write(MIPI_DSI_CLK_TIM,
(dphy->clk_trail | (dphy->clk_post << 8) |
(dphy->clk_trail | ((dphy->clk_post+dphy->hs_trail) << 8) |
(dphy->clk_zero << 16) | (dphy->clk_prepare << 24)));
dsi_phy_write(MIPI_DSI_CLK_TIM1, dphy->clk_pre); /* ?? */
/* 0x050f090d */
@@ -1584,7 +1584,7 @@ static void mipi_dsi_phy_config(struct dsi_phy_s *dphy, unsigned int dsi_ui)
if ((dphy->clk_trail * temp) < t_req_min)
dphy->clk_trail += 1;
t_req_min = 60 * 100 + 52 * t_ui + 10 * 100;
t_req_min = 60 * 100 + 52 * t_ui + 30 * 100;
dphy->clk_post = t_req_min / temp;
if ((dphy->clk_post * temp) < t_req_min)
dphy->clk_post += 1;