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tvin: optimize for game mode
PD#165399: tvin: optimize for game mode Change-Id: Ifcdb6ff8b88f433e4aa07c4b5692dff8ac6134ea Signed-off-by: Dezhi Kong <dezhi.kong@amlogic.com>
This commit is contained in:
@@ -5821,6 +5821,11 @@ static bool need_bypass(struct vframe_s *vf)
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(vf->height > (default_height + 8)))
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return true;
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/*true bypass for 720p above*/
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if ((vf->flag & VFRAME_FLAG_GAME_MODE) &&
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(vf->width > 720))
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return true;
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return false;
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}
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@@ -159,6 +159,9 @@ module_param(tx_op_color_primary, int, 0664);
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MODULE_PARM_DESC(tx_op_color_primary,
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"tx output color_primary");
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unsigned int debug_game_mode_1;
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module_param(debug_game_mode_1, uint, 0664);
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MODULE_PARM_DESC(debug_game_mode_1, "\n debug_game_mode_1\n");
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unsigned int pq_user_value;
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unsigned int hdr_source_type = 0x1;
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@@ -676,7 +679,7 @@ void vpp_get_hist_en(void)
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WRITE_VPP_REG(VI_HIST_GCLK_CTRL, 0xffffffff);
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WRITE_VPP_REG_BITS(VI_HIST_CTRL, 2, VI_HIST_POW_BIT, VI_HIST_POW_WID);
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}
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static unsigned int vpp_luma_max;
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void vpp_get_vframe_hist_info(struct vframe_s *vf)
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{
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unsigned int hist_height, hist_width;
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@@ -838,6 +841,14 @@ void vpp_get_vframe_hist_info(struct vframe_s *vf)
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VI_HIST_ON_BIN_62_BIT, VI_HIST_ON_BIN_62_WID);
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vf->prop.hist.vpp_gamma[63] = READ_VPP_REG_BITS(VI_DNLP_HIST31,
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VI_HIST_ON_BIN_63_BIT, VI_HIST_ON_BIN_63_WID);
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if (debug_game_mode_1 &&
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(vpp_luma_max != vf->prop.hist.vpp_luma_max)) {
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vf->ready_clock_hist[1] = sched_clock();
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pr_info("vpp output done %lld us. luma_max(0x%x-->0x%x)\n",
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vf->ready_clock_hist[1]/1000,
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vpp_luma_max, vf->prop.hist.vpp_luma_max);
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vpp_luma_max = vf->prop.hist.vpp_luma_max;
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}
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}
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static void ioctrl_get_hdr_metadata(struct vframe_s *vf)
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@@ -2171,6 +2171,21 @@ static void vsync_toggle_frame(struct vframe_s *vf)
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#else
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video_vf_put(cur_dispbuf);
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#endif
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if (debug_flag & DEBUG_FLAG_LATENCY) {
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vf->ready_clock[3] = sched_clock();
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pr_info("video toggle latency %lld ms video get latency %lld ms vdin put latency %lld ms. first %lld ms.\n",
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vf->ready_clock[3]/1000,
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vf->ready_clock[2]/1000,
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vf->ready_clock[1]/1000,
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vf->ready_clock[0]/1000);
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cur_dispbuf->ready_clock[4] = sched_clock();
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pr_info("video put latency %lld ms video toggle latency %lld ms video get latency %lld ms vdin put latency %lld ms. first %lld ms.\n",
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cur_dispbuf->ready_clock[4]/1000,
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cur_dispbuf->ready_clock[3]/1000,
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cur_dispbuf->ready_clock[2]/1000,
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cur_dispbuf->ready_clock[1]/1000,
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cur_dispbuf->ready_clock[0]/1000);
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}
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}
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} else
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@@ -3660,6 +3675,9 @@ static inline bool vpts_expire(struct vframe_s *cur_vf,
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if ((freerun_mode == FREERUN_NODUR) || hdmi_in_onvideo)
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return true;
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/*freerun for game mode*/
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if (next_vf->flag & VFRAME_FLAG_GAME_MODE)
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return true;
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if (step_enable) {
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if (step_flag)
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@@ -4783,6 +4801,13 @@ static irqreturn_t vsync_isr_in(int irq, void *dev_id)
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vf = video_vf_get();
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if (!vf)
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break;
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if (debug_flag & DEBUG_FLAG_LATENCY) {
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vf->ready_clock[2] = sched_clock();
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pr_info("video get latency %lld ms vdin put latency %lld ms. first %lld ms.\n",
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vf->ready_clock[2]/1000,
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vf->ready_clock[1]/1000,
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vf->ready_clock[0]/1000);
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}
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if (video_vf_dirty_put(vf))
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break;
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if (vf && hdmiin_frame_check && (vf->source_type ==
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@@ -26,7 +26,7 @@
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#define DEBUG_FLAG_RDMA_WAIT_1 0x40000
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#define DEBUG_FLAG_VSYNC_DONONE 0x80000
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#define DEBUG_FLAG_GOFIELD_MANUL 0x100000
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#define DEBUG_FLAG_LATENCY 0x200000
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/*for video.c's static int debug_flag;*/
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#define VOUT_TYPE_TOP_FIELD 0
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@@ -163,7 +163,8 @@ void vdin_canvas_start_config(struct vdin_dev_s *devp)
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/*backup before roundup*/
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devp->canvas_active_w = devp->canvas_w;
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if (devp->force_yuv444_malloc == 1) {
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if (devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH)
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if ((devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) &&
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(devp->color_depth_mode != 1))
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devp->canvas_w = devp->h_active *
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VDIN_YUV444_10BIT_PER_PIXEL_BYTE;
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else
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@@ -305,7 +306,8 @@ void vdin_canvas_auto_config(struct vdin_dev_s *devp)
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/*backup before roundup*/
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devp->canvas_active_w = devp->canvas_w;
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if (devp->force_yuv444_malloc == 1) {
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if (devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH)
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if ((devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) &&
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(devp->color_depth_mode != 1))
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devp->canvas_w = devp->h_active *
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VDIN_YUV444_10BIT_PER_PIXEL_BYTE;
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else
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@@ -388,17 +390,18 @@ void vdin_canvas_auto_config(struct vdin_dev_s *devp)
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}
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#ifdef CONFIG_CMA
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/* need to be static for pointer use in codec_mm */
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static char vdin_name[6];
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/* return val:1: fail;0: ok */
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unsigned int vdin_cma_alloc(struct vdin_dev_s *devp)
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{
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char vdin_name[6];
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unsigned int mem_size, h_size, v_size;
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int flags = CODEC_MM_FLAGS_CMA_FIRST|CODEC_MM_FLAGS_CMA_CLEAR|
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CODEC_MM_FLAGS_CPU;
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unsigned int max_buffer_num = min_buf_num;
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unsigned int i;
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if (devp->rdma_enable && (devp->game_mode == 0))
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if (devp->rdma_enable)
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max_buffer_num++;
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/*todo: need update if vf_skip_cnt used by other port*/
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if (devp->vfp->skip_vf_num &&
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@@ -431,7 +434,8 @@ unsigned int vdin_cma_alloc(struct vdin_dev_s *devp)
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(devp->format_convert == VDIN_FORMAT_CONVERT_YUV_GBR) ||
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(devp->format_convert == VDIN_FORMAT_CONVERT_YUV_BRG) ||
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(devp->force_yuv444_malloc == 1)) {
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if (devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) {
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if ((devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) &&
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(devp->color_depth_mode != 1)) {
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h_size = roundup(h_size *
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VDIN_YUV444_10BIT_PER_PIXEL_BYTE,
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devp->canvas_align);
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@@ -106,6 +106,10 @@ static int vdin_ctl_dbg;
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module_param(vdin_ctl_dbg, int, 0664);
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MODULE_PARM_DESC(vdin_ctl_dbg, "vdin_ctl_dbg");
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/*bit0/1:game mode enable for vdin0/1*/
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unsigned int game_mode;
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module_param(game_mode, uint, 0664);
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MODULE_PARM_DESC(game_mode, "game_mode");
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static unsigned int vpu_reg_27af = 0x3;
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/***************************Local defines**********************************/
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@@ -1815,7 +1819,7 @@ static inline void vdin_set_wr_ctrl(struct vdin_dev_s *devp,
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/* win_ve */
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wr_bits(offset, VDIN_WR_V_START_END, (v - 1), WR_VEND_BIT, WR_VEND_WID);
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/* hconv_mode */
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wr_bits(offset, VDIN_WR_CTRL, 0, HCONV_MODE_BIT, HCONV_MODE_WID);
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wr_bits(offset, VDIN_WR_CTRL, 2, HCONV_MODE_BIT, HCONV_MODE_WID);
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/* vconv_mode */
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wr_bits(offset, VDIN_WR_CTRL, 0, VCONV_MODE_BIT, VCONV_MODE_WID);
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if (write_format444 == 2) {
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@@ -1914,6 +1918,7 @@ void vdin_set_wr_ctrl_vsync(struct vdin_dev_s *devp,
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} else if (write_format444 == 1) {
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vconv_mode = 3;
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} else {
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hconv_mode = 2;
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swap_cbcr = 0;
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}
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#ifdef CONFIG_AML_RDMA
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@@ -2191,7 +2196,7 @@ static void vdin_set_ldim_max_init(unsigned int offset,
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wr_bits(offset, VDIN_HIST_CTRL, 1, 8, 1);
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}
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#endif
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static unsigned int vdin_luma_max;
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void vdin_set_vframe_prop_info(struct vframe_s *vf,
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struct vdin_dev_s *devp)
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{
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@@ -2390,6 +2395,14 @@ void vdin_set_vframe_prop_info(struct vframe_s *vf,
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/* fetch meas info - For M2 or further chips only, not for M1 chip */
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vf->prop.meas.vs_stamp = devp->stamp;
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vf->prop.meas.vs_cycle = devp->cycle;
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if ((vdin_ctl_dbg & (1 << 8)) &&
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(vdin_luma_max != vf->prop.hist.luma_max)) {
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vf->ready_clock_hist[0] = sched_clock();
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pr_info("vdin write done %lld us. lum_max(0x%x-->0x%x)\n",
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vf->ready_clock_hist[0]/1000,
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vdin_luma_max, vf->prop.hist.luma_max);
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vdin_luma_max = vf->prop.hist.luma_max;
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}
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#if 0
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/*#ifdef CONFIG_AML_LOCAL_DIMMING*/
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/* get ldim max */
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@@ -3784,15 +3797,18 @@ int vdin_event_cb(int type, void *data, void *op_arg)
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}
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index_disp = req->vf->index_disp & 0xff;
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if (index_disp >= VFRAME_DISP_MAX_NUM) {
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if (vdin_ctl_dbg)
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if (vdin_ctl_dbg&(1<<2))
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pr_info("%s:req->vf->index_disp(%d) is overflow!\n",
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__func__, index_disp);
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return -1;
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}
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req->disp_mode = p->disp_mode[index_disp];
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if (game_mode)
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req->disp_mode = VFRAME_DISP_MODE_NULL;
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else
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req->disp_mode = p->disp_mode[index_disp];
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if ((req->req_mode == 1) && (p->skip_vf_num))
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p->disp_mode[index_disp] = VFRAME_DISP_MODE_UNKNOWN;
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if (vdin_ctl_dbg)
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if (vdin_ctl_dbg&(1<<1))
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pr_info("%s(type 0x%x vf index 0x%x)=>disp_mode %d,req_mode:%d\n",
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__func__, type, index_disp, req->disp_mode,
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req->req_mode);
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@@ -105,6 +105,7 @@ struct ldim_max_s {
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};
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#endif
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extern unsigned int game_mode;
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/* ************************************************************************ */
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/* ******** GLOBAL FUNCTION CLAIM ******** */
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@@ -491,8 +491,8 @@ static void vdin_dump_state(struct vdin_dev_s *devp)
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vdin_dump_vf_state(devp->vfp);
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if (vf) {
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pr_info("current vframe index(%u):\n", vf->index);
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pr_info("\t buf(w%u, h%u),type(0x%x, %u), duration(%d),",
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vf->width, vf->height, vf->type, vf->type, vf->duration);
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pr_info("\t buf(w%u, h%u),type(0x%x),flag(0x%x), duration(%d),",
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vf->width, vf->height, vf->type, vf->flag, vf->duration);
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pr_info("\t ratio_control(0x%x).\n", vf->ratio_control);
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pr_info("\t trans fmt %u, left_start_x %u,",
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vf->trans_fmt, vf->left_eye.start_x);
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@@ -518,8 +518,8 @@ static void vdin_dump_state(struct vdin_dev_s *devp)
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curparm->reserved, devp->flags);
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pr_info("max buffer num %u, msr_clk_val:%d.\n",
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devp->canvas_max_num, devp->msr_clk_val);
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pr_info("canvas buffer size %u, rdma_enable: %d, game_mode: %d.\n",
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devp->canvas_max_size, devp->rdma_enable, devp->game_mode);
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pr_info("canvas buffer size %u, rdma_enable: %d.\n",
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devp->canvas_max_size, devp->rdma_enable);
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pr_info("range(%d),csc_cfg:0x%x,urgent_en:%d\n",
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devp->prop.color_fmt_range,
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devp->csc_cfg, devp->urgent_en);
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@@ -133,9 +133,6 @@ static unsigned int vdin_drop_cnt;
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module_param(vdin_drop_cnt, uint, 0664);
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MODULE_PARM_DESC(vdin_drop_cnt, "vdin_drop_cnt");
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static bool game_mode;
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module_param(game_mode, bool, 0664);
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MODULE_PARM_DESC(game_mode, "game_mode");
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static int irq_max_count;
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@@ -262,7 +259,18 @@ void vdin_close_fe(struct vdin_dev_s *devp)
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pr_info("%s ok\n", __func__);
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}
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static void vdin_game_mode_check(struct vdin_dev_s *devp)
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{
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if ((game_mode == 1) &&
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(devp->parm.port != TVIN_PORT_CVBS3)) {
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if (devp->h_active > 720 && ((devp->parm.info.fps == 50) ||
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(devp->parm.info.fps == 60)))
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devp->game_mode = 3;
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else
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devp->game_mode = 1;
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} else
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devp->game_mode = 0;
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}
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/*
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*based on the bellow parameters:
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* a.h_active (vf->width = devp->h_active)
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@@ -298,6 +306,8 @@ static void vdin_vf_init(struct vdin_dev_s *devp)
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vf->index = i;
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vf->width = devp->h_active;
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vf->height = devp->v_active;
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if (devp->game_mode != 0)
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vf->flag |= VFRAME_FLAG_GAME_MODE;
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scan_mode = devp->fmt_info_p->scan_mode;
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if (((scan_mode == TVIN_SCAN_MODE_INTERLACED) &&
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(!(devp->parm.flag & TVIN_PARM_FLAG_2D_TO_3D) &&
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@@ -435,11 +445,7 @@ void vdin_start_dec(struct vdin_dev_s *devp)
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vdin_get_format_convert(devp);
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devp->curr_wr_vfe = NULL;
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devp->game_mode = game_mode;
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if (game_mode)
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devp->vfp->skip_vf_num = 1;
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else
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devp->vfp->skip_vf_num = devp->prop.skip_vf_num;
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devp->vfp->skip_vf_num = devp->prop.skip_vf_num;
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if (devp->vfp->skip_vf_num >= VDIN_CANVAS_MAX_CNT)
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devp->vfp->skip_vf_num = 0;
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devp->canvas_config_mode = canvas_config_mode;
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@@ -487,6 +493,7 @@ void vdin_start_dec(struct vdin_dev_s *devp)
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devp->vfp->size = devp->canvas_max_num;
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vf_pool_init(devp->vfp, devp->vfp->size);
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vdin_game_mode_check(devp);
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vdin_vf_init(devp);
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#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
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if ((devp->dv.dolby_input & (1 << devp->index)) ||
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@@ -1200,14 +1207,14 @@ irqreturn_t vdin_isr(int irq, void *dev_id)
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if (!devp->curr_wr_vfe) {
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devp->curr_wr_vfe = provider_vf_get(devp->vfp);
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devp->curr_wr_vfe->vf.ready_jiffies64 = jiffies_64;
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devp->curr_wr_vfe->vf.ready_clock[0] = sched_clock();
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/*save the first field stamp*/
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devp->stamp = stamp;
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devp->vdin_irq_flag = 3;
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vdin_drop_cnt++;
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goto irq_handled;
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}
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if (devp->last_wr_vfe && (devp->flags&VDIN_FLAG_RDMA_ENABLE) &&
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(devp->game_mode == false)) {
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!(devp->game_mode & (1 << 1))) {
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/*dolby vision metadata process*/
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if (dv_dbg_mask & DV_UPDATE_DATA_MODE_DELBY_WORK
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&& devp->dv.dv_config) {
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@@ -1225,9 +1232,16 @@ irqreturn_t vdin_isr(int irq, void *dev_id)
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} else
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devp->dv.dv_crc_check = true;
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if ((devp->dv.dv_crc_check == true) ||
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(!(dv_dbg_mask & DV_CRC_CHECK)))
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(!(dv_dbg_mask & DV_CRC_CHECK))) {
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provider_vf_put(devp->last_wr_vfe, devp->vfp);
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else {
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if (time_en) {
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devp->last_wr_vfe->vf.ready_clock[1] =
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sched_clock();
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pr_info("vdin put latency %lld us. first %lld us.\n",
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devp->last_wr_vfe->vf.ready_clock[1]/1000,
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devp->last_wr_vfe->vf.ready_clock[0]/1000);
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}
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} else {
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devp->vdin_irq_flag = 15;
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vdin_drop_cnt++;
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goto irq_handled;
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@@ -1369,6 +1383,7 @@ irqreturn_t vdin_isr(int irq, void *dev_id)
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if (!next_wr_vfe) {
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devp->vdin_irq_flag = 14;
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vdin_drop_cnt++;
|
||||
vf_drop_cnt = vdin_drop_cnt;/*avoid do skip*/
|
||||
goto irq_handled;
|
||||
}
|
||||
#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
|
||||
@@ -1384,7 +1399,8 @@ irqreturn_t vdin_isr(int irq, void *dev_id)
|
||||
/*if vdin-nr,di must get
|
||||
* vdin current field type which di pre will read
|
||||
*/
|
||||
if (vdin2nr || (devp->flags & VDIN_FLAG_RDMA_ENABLE))
|
||||
if ((vdin2nr || (devp->flags & VDIN_FLAG_RDMA_ENABLE)) &&
|
||||
!(devp->game_mode & (1 << 1)))
|
||||
curr_wr_vf->type = devp->curr_field_type;
|
||||
else
|
||||
curr_wr_vf->type = last_field_type;
|
||||
@@ -1439,7 +1455,8 @@ irqreturn_t vdin_isr(int irq, void *dev_id)
|
||||
if (devp->auto_ratio_en && (devp->parm.port >= TVIN_PORT_CVBS0) &&
|
||||
(devp->parm.port <= TVIN_PORT_CVBS3))
|
||||
vdin_set_display_ratio(devp, curr_wr_vf);
|
||||
if (devp->flags&VDIN_FLAG_RDMA_ENABLE && (devp->game_mode == false)) {
|
||||
if ((devp->flags&VDIN_FLAG_RDMA_ENABLE) &&
|
||||
!(devp->game_mode & (1 << 1))) {
|
||||
devp->last_wr_vfe = curr_wr_vfe;
|
||||
} else {
|
||||
/*dolby vision metadata process*/
|
||||
@@ -1457,9 +1474,15 @@ irqreturn_t vdin_isr(int irq, void *dev_id)
|
||||
} else
|
||||
devp->dv.dv_crc_check = true;
|
||||
if ((devp->dv.dv_crc_check == true) ||
|
||||
(!(dv_dbg_mask & DV_CRC_CHECK)))
|
||||
(!(dv_dbg_mask & DV_CRC_CHECK))) {
|
||||
provider_vf_put(curr_wr_vfe, devp->vfp);
|
||||
else {
|
||||
if (vdin_dbg_en) {
|
||||
curr_wr_vfe->vf.ready_clock[1] = sched_clock();
|
||||
pr_info("vdin put latency %lld us. first %lld us.\n",
|
||||
curr_wr_vfe->vf.ready_clock[1]/1000,
|
||||
curr_wr_vfe->vf.ready_clock[0]/1000);
|
||||
}
|
||||
} else {
|
||||
devp->vdin_irq_flag = 15;
|
||||
vdin_drop_cnt++;
|
||||
goto irq_handled;
|
||||
@@ -1482,8 +1505,10 @@ irqreturn_t vdin_isr(int irq, void *dev_id)
|
||||
devp->curr_wr_vfe = next_wr_vfe;
|
||||
/* debug for video latency */
|
||||
next_wr_vfe->vf.ready_jiffies64 = jiffies_64;
|
||||
next_wr_vfe->vf.ready_clock[0] = sched_clock();
|
||||
|
||||
if (!(devp->flags&VDIN_FLAG_RDMA_ENABLE) || (devp->game_mode == true)) {
|
||||
if (!(devp->flags&VDIN_FLAG_RDMA_ENABLE) ||
|
||||
(devp->game_mode & (1 << 1))) {
|
||||
#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
|
||||
if (((devp->dv.dolby_input & (1 << devp->index)) ||
|
||||
(devp->dv.dv_flag && is_dolby_vision_enable())) &&
|
||||
@@ -2146,6 +2171,14 @@ static long vdin_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
||||
if (vdin_dbg_en)
|
||||
pr_info("TVIN_IOC_SNOWOFF(%d) ok\n\n", devp->index);
|
||||
break;
|
||||
case TVIN_IOC_GAME_MODE:
|
||||
if (copy_from_user(&game_mode, argp, sizeof(unsigned int))) {
|
||||
ret = -EFAULT;
|
||||
break;
|
||||
}
|
||||
if (vdin_dbg_en)
|
||||
pr_info("TVIN_IOC_GAME_MODE(%d) done\n\n", game_mode);
|
||||
break;
|
||||
case TVIN_IOC_GET_COLOR_RANGE:
|
||||
if (copy_to_user(argp,
|
||||
&color_range_force,
|
||||
@@ -2514,7 +2547,6 @@ static int vdin_drv_probe(struct platform_device *pdev)
|
||||
vdevp->rdma_enable = 1;
|
||||
/*set vdin_dev_s size*/
|
||||
vdevp->vdin_dev_ssize = sizeof(struct vdin_dev_s);
|
||||
vdevp->game_mode = game_mode;
|
||||
vdevp->canvas_config_mode = canvas_config_mode;
|
||||
INIT_DELAYED_WORK(&vdevp->dv.dv_dwork, vdin_dv_dwork);
|
||||
|
||||
|
||||
@@ -45,7 +45,7 @@
|
||||
#include "vdin_vf.h"
|
||||
#include "vdin_regs.h"
|
||||
|
||||
#define VDIN_VER "Ref.2017/011/17"
|
||||
#define VDIN_VER "Ref.2018/04/28"
|
||||
|
||||
/*the counter of vdin*/
|
||||
#define VDIN_MAX_DEVS 2
|
||||
@@ -282,7 +282,12 @@ struct vdin_dev_s {
|
||||
unsigned int color_range_mode;
|
||||
/*auto detect av/atv input ratio*/
|
||||
unsigned int auto_ratio_en;
|
||||
bool game_mode;/*1:game mode for hdmi*/
|
||||
/*
|
||||
*game_mode:
|
||||
*bit0:enable/disable
|
||||
*bit1:for true bypas and put vframe in advance one vsync
|
||||
*/
|
||||
unsigned int game_mode;
|
||||
unsigned int rdma_enable;
|
||||
unsigned int canvas_config_mode;
|
||||
bool prehsc_en;
|
||||
|
||||
@@ -59,8 +59,9 @@ static int sm_print_fmt_chg;
|
||||
static int sm_atv_prestable_fmt;
|
||||
static int sm_print_prestable;
|
||||
|
||||
static bool sm_debug_enable = true;
|
||||
module_param(sm_debug_enable, bool, 0664);
|
||||
/*bit0:general debug bit;bit1:hdmirx color change*/
|
||||
static unsigned int sm_debug_enable = 1;
|
||||
module_param(sm_debug_enable, uint, 0664);
|
||||
MODULE_PARM_DESC(sm_debug_enable,
|
||||
"enable/disable state machine debug message");
|
||||
|
||||
@@ -211,12 +212,13 @@ static void hdmirx_color_fmt_handler(struct vdin_dev_s *devp)
|
||||
(vdin_hdr_flag != pre_vdin_hdr_flag) ||
|
||||
(vdin_fmt_range != pre_vdin_fmt_range) ||
|
||||
(cur_dest_color_fmt != pre_dest_color_fmt)) {
|
||||
pr_info("[smr.%d] cur color fmt(%d->%d), hdr_flag(%d->%d), dest color fmt(%d->%d), csc_cfg:0x%x\n",
|
||||
devp->index,
|
||||
pre_color_fmt, cur_color_fmt,
|
||||
pre_vdin_hdr_flag, vdin_hdr_flag,
|
||||
pre_dest_color_fmt, cur_dest_color_fmt,
|
||||
devp->csc_cfg);
|
||||
if (sm_debug_enable & (1 << 1))
|
||||
pr_info("[smr.%d] cur color fmt(%d->%d), hdr_flag(%d->%d), dest color fmt(%d->%d), csc_cfg:0x%x\n",
|
||||
devp->index,
|
||||
pre_color_fmt, cur_color_fmt,
|
||||
pre_vdin_hdr_flag, vdin_hdr_flag,
|
||||
pre_dest_color_fmt, cur_dest_color_fmt,
|
||||
devp->csc_cfg);
|
||||
vdin_get_format_convert(devp);
|
||||
devp->csc_cfg = 1;
|
||||
} else
|
||||
@@ -671,3 +673,12 @@ enum tvin_sm_status_e tvin_get_sm_status(int index)
|
||||
}
|
||||
EXPORT_SYMBOL(tvin_get_sm_status);
|
||||
|
||||
int tvin_get_av_status(void)
|
||||
{
|
||||
if (tvin_get_sm_status(0) == TVIN_SM_STATUS_STABLE)
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
EXPORT_SYMBOL(tvin_get_av_status);
|
||||
|
||||
|
||||
@@ -38,7 +38,7 @@
|
||||
|
||||
#define VF_FLAG_NORMAL_FRAME 0x00000001
|
||||
#define VF_FLAG_FREEZED_FRAME 0x00000002
|
||||
#define VFRAME_DISP_MAX_NUM 10
|
||||
#define VFRAME_DISP_MAX_NUM 20
|
||||
#define VDIN_VF_POOL_FREEZE 0x00000001
|
||||
#define ISR_LOG_EN
|
||||
|
||||
|
||||
@@ -430,7 +430,7 @@ struct tvafe_pin_mux_s {
|
||||
enum tvin_force_color_range_e)
|
||||
#define TVIN_IOC_SET_COLOR_RANGE _IOW(_TM_T, 0X4a,\
|
||||
enum tvin_force_color_range_e)
|
||||
|
||||
#define TVIN_IOC_GAME_MODE _IOW(_TM_T, 0x4b, unsigned int)
|
||||
/* TVAFE */
|
||||
#define TVIN_IOC_S_AFE_VGA_PARM _IOW(_TM_T, 0x16, struct tvafe_vga_parm_s)
|
||||
#define TVIN_IOC_G_AFE_VGA_PARM _IOR(_TM_T, 0x17, struct tvafe_vga_parm_s)
|
||||
|
||||
@@ -74,6 +74,7 @@
|
||||
#define VFRAME_FLAG_HIGH_BANDWIDTH 4
|
||||
#define VFRAME_FLAG_ERROR_RECOVERY 8
|
||||
#define VFRAME_FLAG_SYNCFRAME 0x10
|
||||
#define VFRAME_FLAG_GAME_MODE 0x20
|
||||
|
||||
enum pixel_aspect_ratio_e {
|
||||
PIXEL_ASPECT_RATIO_1_1,
|
||||
@@ -321,6 +322,8 @@ struct vframe_s {
|
||||
/* pixel aspect ratio */
|
||||
enum pixel_aspect_ratio_e pixel_ratio;
|
||||
u64 ready_jiffies64; /* ready from decode on jiffies_64 */
|
||||
long long ready_clock[5];/*ns*/
|
||||
long long ready_clock_hist[2];/*ns*/
|
||||
atomic_t use_cnt;
|
||||
u32 frame_dirty;
|
||||
/*
|
||||
|
||||
@@ -54,7 +54,7 @@ struct provider_aux_req_s {
|
||||
struct provider_disp_mode_req_s {
|
||||
/*input*/
|
||||
struct vframe_s *vf;
|
||||
unsigned int req_mode;/*0:peak;1:get*/
|
||||
unsigned int req_mode;/*0:get;1:check*/
|
||||
/*output*/
|
||||
enum vframe_disp_mode_e disp_mode;
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user