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vpu: add vpu support for txlx

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PD#154260: vpu: add vpu support for txlx

Update dts for all platforms.

1. add support for txlx
2. add clktree support for clk change
3. remove unused vpu module for mem_pd
4. remove vpu_parent "vid_pll","mpll1","mpll2"

Change-Id: I43aa2435305fd02664ae825bc2f62664ffb526be
Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>
This commit is contained in:
Evoke Zhang
2017-11-14 09:22:38 +08:00
committed by Jianxin Pan
parent c4e118637c
commit 9585305649
20 changed files with 1086 additions and 1271 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
MAINTAINERS
View File

@@ -14147,6 +14147,10 @@ AMLOGIC LED DRVIER
M: Peipeng Zhao <peipeng.zhao@amlogic.com>
F: Documentation/leds/leds-is31fl32xx.txt
AMLOGIC VPU DRIVER
M: Evoke Zhang <evoke.zhang@amlogic.com>
F: drivers/amlogic/media/common/vpu/*
AMLOGIC ADD P241 V2 DTS
M: Siming Chen <siming.chen@amlogic.com>
F: arch/arm64/boot/dts/amlogic/gxl_p241_v2-1g.dts

16
arch/arm64/boot/dts/amlogic/axg_pxp.dts
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@@ -202,12 +202,16 @@
compatible = "amlogic, vpu";
dev_name = "vpu";
status = "ok";
clocks = <&clkc CLKID_VPU_MUX
&clkc CLKID_VAPB_MUX
&clkc CLKID_VPU_INTR>;
clock-names = "vpu_clk",
"vapb_clk",
"vpu_intr";
clocks = <&clkc CLKID_VAPB_MUX
&clkc CLKID_VPU_INTR
&clkc CLKID_VPU_P0_MUX
&clkc CLKID_VPU_P1_MUX
&clkc CLKID_VPU_MUX>;
clock-names = "vapb_clk",
"vpu_intr",
"vpu_clk0",
"vpu_clk1",
"vpu_clk";
clk_level = <3>;
/* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */
};

20
arch/arm64/boot/dts/amlogic/axg_s400.dts
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@@ -421,15 +421,19 @@
};
vpu {
compatible = "amlogic, vpu";
compatible = "amlogic, vpu-axg";
dev_name = "vpu";
status = "ok";
clocks = <&clkc CLKID_VPU_MUX
&clkc CLKID_VAPB_MUX
&clkc CLKID_VPU_INTR>;
clock-names = "vpu_clk",
"vapb_clk",
"vpu_intr";
status = "okay";
clocks = <&clkc CLKID_VAPB_MUX>,
<&clkc CLKID_VPU_INTR>,
<&clkc CLKID_VPU_P0_COMP>,
<&clkc CLKID_VPU_P1_COMP>,
<&clkc CLKID_VPU_MUX>;
clock-names = "vapb_clk",
"vpu_intr",
"vpu_clk0",
"vpu_clk1",
"vpu_clk";
clk_level = <3>;
/* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */
};

20
arch/arm64/boot/dts/amlogic/axg_s400_v03.dts
View File

@@ -421,15 +421,19 @@
};
vpu {
compatible = "amlogic, vpu";
compatible = "amlogic, vpu-axg";
dev_name = "vpu";
status = "ok";
clocks = <&clkc CLKID_VPU_MUX
&clkc CLKID_VAPB_MUX
&clkc CLKID_VPU_INTR>;
clock-names = "vpu_clk",
"vapb_clk",
"vpu_intr";
status = "okay";
clocks = <&clkc CLKID_VAPB_MUX>,
<&clkc CLKID_VPU_INTR>,
<&clkc CLKID_VPU_P0_COMP>,
<&clkc CLKID_VPU_P1_COMP>,
<&clkc CLKID_VPU_MUX>;
clock-names = "vapb_clk",
"vpu_intr",
"vpu_clk0",
"vpu_clk1",
"vpu_clk";
clk_level = <3>;
/* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */
};

20
arch/arm64/boot/dts/amlogic/axg_s400emmc.dts
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@@ -417,15 +417,19 @@
};
vpu {
compatible = "amlogic, vpu";
compatible = "amlogic, vpu-axg";
dev_name = "vpu";
status = "ok";
clocks = <&clkc CLKID_VPU_MUX
&clkc CLKID_VAPB_MUX
&clkc CLKID_VPU_INTR>;
clock-names = "vpu_clk",
"vapb_clk",
"vpu_intr";
status = "okay";
clocks = <&clkc CLKID_VAPB_MUX>,
<&clkc CLKID_VPU_INTR>,
<&clkc CLKID_VPU_P0_COMP>,
<&clkc CLKID_VPU_P1_COMP>,
<&clkc CLKID_VPU_MUX>;
clock-names = "vapb_clk",
"vpu_intr",
"vpu_clk0",
"vpu_clk1",
"vpu_clk";
clk_level = <3>;
/* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */
};

20
arch/arm64/boot/dts/amlogic/axg_s400emmc_v03.dts
View File

@@ -417,15 +417,19 @@
};
vpu {
compatible = "amlogic, vpu";
compatible = "amlogic, vpu-axg";
dev_name = "vpu";
status = "ok";
clocks = <&clkc CLKID_VPU_MUX
&clkc CLKID_VAPB_MUX
&clkc CLKID_VPU_INTR>;
clock-names = "vpu_clk",
"vapb_clk",
"vpu_intr";
status = "okay";
clocks = <&clkc CLKID_VAPB_MUX>,
<&clkc CLKID_VPU_INTR>,
<&clkc CLKID_VPU_P0_COMP>,
<&clkc CLKID_VPU_P1_COMP>,
<&clkc CLKID_VPU_MUX>;
clock-names = "vapb_clk",
"vpu_intr",
"vpu_clk0",
"vpu_clk1",
"vpu_clk";
clk_level = <3>;
/* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */
};

22
arch/arm64/boot/dts/amlogic/mesongxl.dtsi
View File

@@ -271,15 +271,21 @@
};
vpu {
compatible = "amlogic, vpu";
compatible = "amlogic, vpu-gxl";
dev_name = "vpu";
status = "ok";
clocks = <&clkc CLKID_VPU_MUX
&clkc CLKID_VAPB_MUX
&clkc CLKID_VPU_INTR>;
clock-names = "vpu_clk",
"vapb_clk",
"vpu_intr";
status = "okay";
clocks = <&clkc CLKID_VAPB_MUX>,
<&clkc CLKID_VPU_INTR>,
<&clkc CLKID_GP0_PLL>,
<&clkc CLKID_VPU_P0_COMP>,
<&clkc CLKID_VPU_P1_COMP>,
<&clkc CLKID_VPU_MUX>;
clock-names = "vapb_clk",
"vpu_intr",
"gp_pll",
"vpu_clk0",
"vpu_clk1",
"vpu_clk";
clk_level = <7>;
/* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */
/* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */

22
arch/arm64/boot/dts/amlogic/mesongxm.dtsi
View File

@@ -354,15 +354,21 @@
};
vpu {
compatible = "amlogic, vpu";
compatible = "amlogic, vpu-gxm";
dev_name = "vpu";
status = "ok";
clocks = <&clkc CLKID_VPU_MUX
&clkc CLKID_VAPB_MUX
&clkc CLKID_VPU_INTR>;
clock-names = "vpu_clk",
"vapb_clk",
"vpu_intr";
status = "okay";
clocks = <&clkc CLKID_VAPB_MUX>,
<&clkc CLKID_VPU_INTR>,
<&clkc CLKID_GP0_PLL>,
<&clkc CLKID_VPU_P0_COMP>,
<&clkc CLKID_VPU_P1_COMP>,
<&clkc CLKID_VPU_MUX>;
clock-names = "vapb_clk",
"vpu_intr",
"gp_pll",
"vpu_clk0",
"vpu_clk1",
"vpu_clk";
clk_level = <7>;
/* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */
/* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */

4
drivers/amlogic/clk/axg/axg_clk_media.c
View File

@@ -79,8 +79,8 @@ static struct clk_hw *dsi_meas_clk_hws[] = {
};
static const char * const vpu_parent_names[] = { "fclk_div4",
"fclk_div3", "fclk_div5", "fclk_div7", "mpll1", "null",
"mpll2", "null"};
"fclk_div3", "fclk_div5", "fclk_div7", "null", "null",
"null", "null"};
/* cts_vpu_clk */
static struct clk_mux vpu_p0_mux = {

2
drivers/amlogic/clk/gxl/clk_media.c
View File

@@ -360,7 +360,7 @@ static struct clk_hw *hevc_clk_hws[] = {
};
const char *vpu_parent_names[] = { "fclk_div4", "fclk_div3", "fclk_div5",
"fclk_div7", "mpll1", "vid_pll_clk", "mpll2", "gp1_pll"};
"fclk_div7", "null", "null", "null", "gp1_pll"};
/* cts_vpu_clk */
static struct clk_mux vpu_p0_mux = {

2
drivers/amlogic/media/common/vpu/Makefile
View File

@@ -1,2 +1,2 @@
obj-$(CONFIG_AMLOGIC_VPU) += vpu.o vpu_ctrl.o vpu_reg.o
obj-$(CONFIG_AMLOGIC_VPU) += vpu.o vpu_reg.o

847
drivers/amlogic/media/common/vpu/vpu.c
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File diff suppressed because it is too large Load Diff

59
drivers/amlogic/media/common/vpu/vpu.h
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@@ -17,6 +17,8 @@
#ifndef __VPU_PARA_H__
#define __VPU_PARA_H__
#include <linux/clk.h>
#include <linux/clk-provider.h>
/*#define VPU_DEBUG_PRINT*/
@@ -28,38 +30,55 @@ enum vpu_chip_e {
VPU_CHIP_GXTVBB,
VPU_CHIP_GXL,
VPU_CHIP_GXM,
VPU_CHIP_TXL,
VPU_CHIP_TXLX,
VPU_CHIP_AXG,
VPU_CHIP_MAX,
};
/*
* static char *vpu_chip_name[] = {
* "gxbb",
* "gxtvbb",
* "gxl",
* "gxm",
* "txl",
* "invalid",
* };
*/
struct vpu_ctrl_s {
unsigned int vmod;
unsigned int reg;
unsigned int bit;
unsigned int len;
};
struct vpu_data_s {
enum vpu_chip_e chip_type;
const char *chip_name;
unsigned char clk_level_dft;
unsigned char clk_level_max;
unsigned char gp_pll_valid;
unsigned char mem_pd_reg1_valid;
unsigned char mem_pd_reg2_valid;
unsigned int mem_pd_table_cnt;
unsigned int clk_gate_table_cnt;
struct vpu_ctrl_s *mem_pd_table;
struct vpu_ctrl_s *clk_gate_table;
};
struct vpu_conf_s {
unsigned int clk_level_dft;
unsigned int clk_level_max;
unsigned int clk_level;
unsigned int fclk_type;
unsigned int mem_pd0;
unsigned int mem_pd1;
struct vpu_data_s *data;
unsigned int clk_level;
unsigned int mem_pd0;
unsigned int mem_pd1;
unsigned int mem_pd2;
/* clktree */
struct clk *gp_pll;
struct clk *vpu_clk0;
struct clk *vpu_clk1;
struct clk *vpu_clk;
unsigned int *clk_vmod;
};
/* ************************************************ */
extern struct vpu_conf_s vpu_conf;
extern enum vpu_chip_e vpu_chip_type;
extern int vpu_debug_print_flag;
extern int vpu_ioremap(void);
extern int vpu_chip_valid_check(void);
extern void vpu_ctrl_probe(void);

91
drivers/amlogic/media/common/vpu/vpu_clk.h
View File

@@ -1,91 +0,0 @@
/*
* drivers/amlogic/media/common/vpu/vpu_clk.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef __VPU_CLK_H__
#define __VPU_CLK_H__
/* #define LIMIT_VPU_CLK_LOW */
/* ************************************************ */
/* VPU frequency table, important. DO NOT modify!! */
/* ************************************************ */
#define CLK_FPLL_FREQ 2000 /* MHz */
/* GXBB */
/* freq max=666M, default=666M */
#define CLK_LEVEL_DFT_GXBB 7
#define CLK_LEVEL_MAX_GXBB 8
/* GXTVBB */
/* freq max=666M, default=666M */
#define CLK_LEVEL_DFT_GXTVBB 7
#define CLK_LEVEL_MAX_GXTVBB 8
/* GXL */
/* freq max=666M, default=666M */
#define CLK_LEVEL_DFT_GXL 7
#define CLK_LEVEL_MAX_GXL 8
/* GXM */
/* freq max=666M, default=666M */
#define CLK_LEVEL_DFT_GXM 7
#define CLK_LEVEL_MAX_GXM 8
/* TXL */
/* freq max=666M, default=666M */
#define CLK_LEVEL_DFT_TXL 7
#define CLK_LEVEL_MAX_TXL 8
/* AXG */
/* freq max=250M, default=250M */
#define CLK_LEVEL_DFT_AXG 3
#define CLK_LEVEL_MAX_AXG 4
/* vpu clk setting */
enum vpu_mux_e {
FCLK_DIV4 = 0,
FCLK_DIV3,
FCLK_DIV5,
FCLK_DIV7,
MPLL_CLK1,
VID_PLL_CLK,
VID2_PLL_CLK,
GPLL_CLK,
};
static unsigned int fclk_div_table[] = {
4, /* mux 0 */
3, /* mux 1 */
5, /* mux 2 */
7, /* mux 3 */
2, /* invalid */
};
/* gxbb, gxtvbb, gxl, gxm, txl, axg, fpll=2000M */
static unsigned int vpu_clk_table[10][3] = {
/* frequency clk_mux div */
{100000000, FCLK_DIV5, 3}, /* 0 */
{166667000, FCLK_DIV3, 3}, /* 1 */
{200000000, FCLK_DIV5, 1}, /* 2 */
{250000000, FCLK_DIV4, 1}, /* 3 */
{333333000, FCLK_DIV3, 1}, /* 4 */
{400000000, FCLK_DIV5, 0}, /* 5 */
{500000000, FCLK_DIV4, 0}, /* 6 */
{666667000, FCLK_DIV3, 0}, /* 7 */
{696000000, GPLL_CLK, 0}, /* 8 */
{850000000, GPLL_CLK, 0}, /* 9 */ /* invalid */
};
/* ************************************************ */
#endif

630
drivers/amlogic/media/common/vpu/vpu_ctrl.c
View File

@@ -1,630 +0,0 @@
/*
* drivers/amlogic/media/common/vpu/vpu_ctrl.c
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/amlogic/media/vpu/vpu.h>
#include "vpu_reg.h"
#include "vpu.h"
#include "vpu_module.h"
static spinlock_t vpu_mem_lock;
static spinlock_t vpu_clk_gate_lock;
/* *********************************************** */
/* VPU_MEM_PD control */
/* *********************************************** */
/*
* Function: switch_vpu_mem_pd_vmod
* switch vpu memory power down by specified vmod
*
* Parameters:
* vmod - unsigned int, must be the following constants:
* VPU_MOD, supported by vpu_mod_e
* flag - int, on/off switch flag, must be one of the following constants:
* VPU_MEM_POWER_ON
* VPU_MEM_POWER_DOWN
*
* Example:
* switch_vpu_mem_pd_vmod(VPU_VENCP, VPU_MEM_POWER_ON);
* switch_vpu_mem_pd_vmod(VPU_VIU_OSD1, VPU_MEM_POWER_DOWN);
*
*/
static void switch_vpu_mem_pd_gx(unsigned int vmod, int flag)
{
unsigned long flags = 0;
unsigned int _reg0, _reg1, _reg2;
unsigned int val;
spin_lock_irqsave(&vpu_mem_lock, flags);
val = (flag == VPU_MEM_POWER_ON) ? 0 : 3;
_reg0 = HHI_VPU_MEM_PD_REG0;
_reg1 = HHI_VPU_MEM_PD_REG1;
_reg2 = HHI_VPU_MEM_PD_REG2;
switch (vmod) {
case VPU_VIU_OSD1:
vpu_hiu_setb(_reg0, val, 0, 2);
break;
case VPU_VIU_OSD2:
vpu_hiu_setb(_reg0, val, 2, 2);
break;
case VPU_VIU_VD1:
vpu_hiu_setb(_reg0, val, 4, 2);
break;
case VPU_VIU_VD2:
vpu_hiu_setb(_reg0, val, 6, 2);
break;
case VPU_VIU_CHROMA:
vpu_hiu_setb(_reg0, val, 8, 2);
break;
case VPU_VIU_OFIFO:
vpu_hiu_setb(_reg0, val, 10, 2);
break;
case VPU_VIU_SCALE:
vpu_hiu_setb(_reg0, val, 12, 2);
break;
case VPU_VIU_OSD_SCALE:
vpu_hiu_setb(_reg0, val, 14, 2);
break;
case VPU_VIU_VDIN0:
vpu_hiu_setb(_reg0, val, 16, 2);
break;
case VPU_VIU_VDIN1:
vpu_hiu_setb(_reg0, val, 18, 2);
break;
case VPU_PIC_ROT1:
case VPU_VIU_SRSCL:
vpu_hiu_setb(_reg0, val, 20, 2);
break;
case VPU_PIC_ROT2:
case VPU_VIU_OSDSR:
case VPU_AFBC_DEC1:
vpu_hiu_setb(_reg0, val, 22, 2);
break;
case VPU_PIC_ROT3:
vpu_hiu_setb(_reg0, val, 24, 2);
break;
case VPU_DI_PRE:
vpu_hiu_setb(_reg0, val, 26, 2);
break;
case VPU_DI_POST:
vpu_hiu_setb(_reg0, val, 28, 2);
break;
case VPU_SHARP:
vpu_hiu_setb(_reg0, val, 30, 2);
break;
case VPU_VIU2_OSD1:
vpu_hiu_setb(_reg1, val, 0, 2);
break;
case VPU_VIU2_OSD2:
vpu_hiu_setb(_reg1, val, 2, 2);
break;
case VPU_VIU2_VD1:
vpu_hiu_setb(_reg1, val, 4, 2);
break;
case VPU_VIU2_CHROMA:
vpu_hiu_setb(_reg1, val, 6, 2);
break;
case VPU_VIU2_OFIFO:
vpu_hiu_setb(_reg1, val, 8, 2);
break;
case VPU_VIU2_SCALE:
vpu_hiu_setb(_reg1, val, 10, 2);
break;
case VPU_VIU2_OSD_SCALE:
vpu_hiu_setb(_reg1, val, 12, 2);
break;
case VPU_VDIN_AM_ASYNC:
case VPU_VPU_ARB:
vpu_hiu_setb(_reg1, val, 14, 2);
break;
case VPU_VDISP_AM_ASYNC:
case VPU_AFBC_DEC:
case VPU_OSD1_AFBCD:
case VPU_AFBC_DEC0:
vpu_hiu_setb(_reg1, val, 16, 2);
break;
case VPU_VENCP:
vpu_hiu_setb(_reg1, val, 20, 2);
break;
case VPU_VENCL:
vpu_hiu_setb(_reg1, val, 22, 2);
break;
case VPU_VENCI:
vpu_hiu_setb(_reg1, val, 24, 2);
break;
case VPU_ISP:
vpu_hiu_setb(_reg1, val, 26, 2);
break;
case VPU_CVD2:
case VPU_LDIM_STTS:
vpu_hiu_setb(_reg1, val, 28, 2);
break;
case VPU_ATV_DMD:
case VPU_XVYCC_LUT:
vpu_hiu_setb(_reg1, val, 30, 2);
break;
case VPU_VIU1_WM:
if ((vpu_chip_type == VPU_CHIP_GXL) ||
(vpu_chip_type == VPU_CHIP_GXM) ||
(vpu_chip_type == VPU_CHIP_TXL)) {
vpu_hiu_setb(_reg2, val, 0, 2);
}
break;
default:
VPUPR("switch_vpu_mem_pd: unsupport vpu mod: %d\n", vmod);
break;
}
spin_unlock_irqrestore(&vpu_mem_lock, flags);
}
static void switch_vpu_mem_pd_axg(unsigned int vmod, int flag)
{
unsigned long flags = 0;
unsigned int _reg0;
unsigned int val;
spin_lock_irqsave(&vpu_mem_lock, flags);
val = (flag == VPU_MEM_POWER_ON) ? 0 : 3;
_reg0 = HHI_VPU_MEM_PD_REG0;
switch (vmod) {
case VPU_VIU_OSD1:
vpu_hiu_setb(_reg0, val, 0, 2);
break;
case VPU_VIU_OFIFO:
vpu_hiu_setb(_reg0, val, 2, 2);
break;
case VPU_VPU_ARB:
vpu_hiu_setb(_reg0, val, 4, 2);
break;
case VPU_VENCI:
vpu_hiu_setb(_reg0, val, 6, 2);
break;
default:
VPUPR("switch_vpu_mem_pd: unsupport vpu mod: %d\n", vmod);
break;
}
spin_unlock_irqrestore(&vpu_mem_lock, flags);
}
void switch_vpu_mem_pd_vmod(unsigned int vmod, int flag)
{
int ret = 0;
ret = vpu_chip_valid_check();
if (ret)
return;
switch (vpu_chip_type) {
case VPU_CHIP_AXG:
switch_vpu_mem_pd_axg(vmod, flag);
break;
default:
switch_vpu_mem_pd_gx(vmod, flag);
break;
}
if (vpu_debug_print_flag) {
VPUPR("switch_vpu_mem_pd: %s %s\n",
vpu_mod_table[vmod],
((flag == VPU_MEM_POWER_ON) ? "ON" : "OFF"));
dump_stack();
}
}
/*
* Function: get_vpu_mem_pd_vmod
* switch vpu memory power down by specified vmod
*
* Parameters:
* vmod - unsigned int, must be the following constants:
* VPU_MOD, supported by vpu_mod_e
*
* Returns:
* int, 0 for power on, 1 for power down, -1 for error
*
* Example:
* ret = get_vpu_mem_pd_vmod(VPU_VENCP);
* ret = get_vpu_mem_pd_vmod(VPU_VIU_OSD1);
*
*/
#define VPU_MEM_PD_ERR 0xffff
static int get_vpu_mem_pd_gx(unsigned int vmod)
{
unsigned int _reg0, _reg1, _reg2;
unsigned int val = VPU_MEM_PD_ERR;
_reg0 = HHI_VPU_MEM_PD_REG0;
_reg1 = HHI_VPU_MEM_PD_REG1;
_reg2 = HHI_VPU_MEM_PD_REG2;
switch (vmod) {
case VPU_VIU_OSD1:
val = vpu_hiu_getb(_reg0, 0, 2);
break;
case VPU_VIU_OSD2:
val = vpu_hiu_getb(_reg0, 2, 2);
break;
case VPU_VIU_VD1:
val = vpu_hiu_getb(_reg0, 4, 2);
break;
case VPU_VIU_VD2:
val = vpu_hiu_getb(_reg0, 6, 2);
break;
case VPU_VIU_CHROMA:
val = vpu_hiu_getb(_reg0, 8, 2);
break;
case VPU_VIU_OFIFO:
val = vpu_hiu_getb(_reg0, 10, 2);
break;
case VPU_VIU_SCALE:
val = vpu_hiu_getb(_reg0, 12, 2);
break;
case VPU_VIU_OSD_SCALE:
val = vpu_hiu_getb(_reg0, 14, 2);
break;
case VPU_VIU_VDIN0:
val = vpu_hiu_getb(_reg0, 16, 2);
break;
case VPU_VIU_VDIN1:
val = vpu_hiu_getb(_reg0, 18, 2);
break;
case VPU_PIC_ROT1:
case VPU_VIU_SRSCL:
val = vpu_hiu_getb(_reg0, 20, 2);
break;
case VPU_PIC_ROT2:
case VPU_VIU_OSDSR:
case VPU_AFBC_DEC1:
val = vpu_hiu_getb(_reg0, 22, 2);
break;
case VPU_PIC_ROT3:
val = vpu_hiu_getb(_reg0, 24, 2);
break;
case VPU_DI_PRE:
val = vpu_hiu_getb(_reg0, 26, 2);
break;
case VPU_DI_POST:
val = vpu_hiu_getb(_reg0, 28, 2);
break;
case VPU_SHARP:
val = vpu_hiu_getb(_reg0, 30, 2);
break;
case VPU_VIU2_OSD1:
val = vpu_hiu_getb(_reg1, 0, 2);
break;
case VPU_VIU2_OSD2:
val = vpu_hiu_getb(_reg1, 2, 2);
break;
case VPU_VIU2_VD1:
val = vpu_hiu_getb(_reg1, 4, 2);
break;
case VPU_VIU2_CHROMA:
val = vpu_hiu_getb(_reg1, 6, 2);
break;
case VPU_VIU2_OFIFO:
val = vpu_hiu_getb(_reg1, 8, 2);
break;
case VPU_VIU2_SCALE:
val = vpu_hiu_getb(_reg1, 10, 2);
break;
case VPU_VIU2_OSD_SCALE:
val = vpu_hiu_getb(_reg1, 12, 2);
break;
case VPU_VDIN_AM_ASYNC:
case VPU_VPU_ARB:
val = vpu_hiu_getb(_reg1, 14, 2);
break;
case VPU_VDISP_AM_ASYNC:
case VPU_AFBC_DEC:
case VPU_OSD1_AFBCD:
case VPU_AFBC_DEC0:
val = vpu_hiu_getb(_reg1, 16, 2);
break;
case VPU_VENCP:
val = vpu_hiu_getb(_reg1, 20, 2);
break;
case VPU_VENCL:
val = vpu_hiu_getb(_reg1, 22, 2);
break;
case VPU_VENCI:
val = vpu_hiu_getb(_reg1, 24, 2);
break;
case VPU_ISP:
val = vpu_hiu_getb(_reg1, 26, 2);
break;
case VPU_CVD2:
case VPU_LDIM_STTS:
val = vpu_hiu_getb(_reg1, 28, 2);
break;
case VPU_ATV_DMD:
case VPU_XVYCC_LUT:
val = vpu_hiu_getb(_reg1, 30, 2);
break;
case VPU_VIU1_WM:
if ((vpu_chip_type == VPU_CHIP_GXL) ||
(vpu_chip_type == VPU_CHIP_GXM) ||
(vpu_chip_type == VPU_CHIP_TXL)) {
val = vpu_hiu_getb(_reg2, 0, 2);
} else {
val = VPU_MEM_PD_ERR;
}
break;
default:
val = VPU_MEM_PD_ERR;
break;
}
return val;
}
static int get_vpu_mem_pd_axg(unsigned int vmod)
{
unsigned int _reg0;
unsigned int val = VPU_MEM_PD_ERR;
_reg0 = HHI_VPU_MEM_PD_REG0;
switch (vmod) {
case VPU_VIU_OSD1:
val = vpu_hiu_getb(_reg0, 0, 2);
break;
case VPU_VIU_OFIFO:
val = vpu_hiu_getb(_reg0, 2, 2);
break;
case VPU_VPU_ARB:
val = vpu_hiu_getb(_reg0, 4, 2);
break;
case VPU_VENCL:
val = vpu_hiu_getb(_reg0, 6, 2);
break;
default:
val = VPU_MEM_PD_ERR;
break;
}
return val;
}
int get_vpu_mem_pd_vmod(unsigned int vmod)
{
int ret = 0;
ret = vpu_chip_valid_check();
if (ret)
return -1;
switch (vpu_chip_type) {
case VPU_CHIP_AXG:
ret = get_vpu_mem_pd_axg(vmod);
break;
default:
ret = get_vpu_mem_pd_gx(vmod);
break;
}
if (ret == 0)
return VPU_MEM_POWER_ON;
else if ((ret == 0x3) || (ret == 0xf))
return VPU_MEM_POWER_DOWN;
else
return -1;
}
/* *********************************************** */
/* VPU_CLK_GATE control */
/* *********************************************** */
/*
* Function: switch_vpu_clk_gate_vmod
* switch vpu clk gate by specified vmod
*
* Parameters:
* vmod - unsigned int, must be the following constants:
* VPU_MOD, supported by vpu_mod_e
* flag - int, on/off switch flag, must be one of the following constants:
* VPU_CLK_GATE_ON
* VPU_CLK_GATE_OFF
*
* Example:
* switch_vpu_clk_gate_vmod(VPU_VENCP, VPU_CLK_GATE_ON);
* switch_vpu_clk_gate_vmod(VPU_VPP, VPU_CLK_GATE_OFF);
*
*/
void switch_vpu_clk_gate_vmod(unsigned int vmod, int flag)
{
unsigned long flags = 0;
unsigned int val;
int ret = 0;
ret = vpu_chip_valid_check();
if (ret)
return;
spin_lock_irqsave(&vpu_clk_gate_lock, flags);
val = (flag == VPU_CLK_GATE_ON) ? 1 : 0;
switch (vmod) {
case VPU_VPU_TOP:
vpu_vcbus_setb(VPU_CLK_GATE, val, 1, 1); /* vpu_system_clk */
break;
case VPU_VPU_CLKB:
if ((vpu_chip_type == VPU_CHIP_GXTVBB) ||
(vpu_chip_type == VPU_CHIP_GXL) ||
(vpu_chip_type == VPU_CHIP_GXM) ||
(vpu_chip_type == VPU_CHIP_TXL)) {
/* clkb_gen_en */
vpu_vcbus_setb(VPU_CLK_GATE, val, 17, 1);
}
if ((vpu_chip_type == VPU_CHIP_GXBB) ||
(vpu_chip_type == VPU_CHIP_GXTVBB) ||
(vpu_chip_type == VPU_CHIP_GXL) ||
(vpu_chip_type == VPU_CHIP_GXM) ||
(vpu_chip_type == VPU_CHIP_TXL)) {
/* clkb_gate */
vpu_vcbus_setb(VPU_CLK_GATE, val, 16, 1);
}
break;
case VPU_RDMA:
if ((vpu_chip_type == VPU_CHIP_GXBB) ||
(vpu_chip_type == VPU_CHIP_GXTVBB) ||
(vpu_chip_type == VPU_CHIP_GXL) ||
(vpu_chip_type == VPU_CHIP_GXM) ||
(vpu_chip_type == VPU_CHIP_TXL)) {
vpu_vcbus_setb(VPU_CLK_GATE, val, 15, 1); /* rdma_clk */
}
break;
case VPU_VLOCK:
vpu_vcbus_setb(VPU_CLK_GATE, val, 14, 1);
break;
case VPU_MISC:
vpu_vcbus_setb(VPU_CLK_GATE, val, 6, 1); /* hs,vs,interrupt */
break;
case VPU_VENC_DAC:
/* clk for dac(r/w reg) */
/*vpu_vcbus_setb(VPU_CLK_GATE, val, 12, 1);*/
vpu_hiu_setb(HHI_GCLK_OTHER, val, 10, 1); /* dac top clk */
break;
case VPU_VENCP:
if (flag == VPU_CLK_GATE_ON) {
vpu_vcbus_set_mask(VPU_CLK_GATE,
((1 << 3) || (1 << 0)));
vpu_hiu_set_mask(HHI_GCLK_OTHER,
((1 << 9) || (0x3 << 3)));
} else {
vpu_vcbus_clr_mask(VPU_CLK_GATE,
((1 << 3) || (1 << 0)));
vpu_hiu_clr_mask(HHI_GCLK_OTHER,
((1 << 9) || (0x3 << 3)));
}
break;
case VPU_VENCL:
if (flag == VPU_CLK_GATE_ON) {
vpu_vcbus_set_mask(VPU_CLK_GATE, (0x3 << 4));
vpu_hiu_set_mask(HHI_GCLK_OTHER, (0x7 << 23));
} else {
vpu_vcbus_clr_mask(VPU_CLK_GATE, (0x3 << 4));
vpu_hiu_clr_mask(HHI_GCLK_OTHER, (0x7 << 23));
}
break;
case VPU_VENCI:
if (flag == VPU_CLK_GATE_ON) {
vpu_vcbus_set_mask(VPU_CLK_GATE, (0x3 << 10));
vpu_hiu_set_mask(HHI_GCLK_OTHER,
((1 << 8) | (0x3 << 1)));
} else {
vpu_vcbus_clr_mask(VPU_CLK_GATE, (0x3 << 10));
vpu_hiu_clr_mask(HHI_GCLK_OTHER,
((1 << 8) | (0x3 << 1)));
}
break;
case VPU_VIU_VDIN0:
if (flag == VPU_CLK_GATE_ON) {
vpu_vcbus_set_mask(VDIN0_COM_GCLK_CTRL, 0x3f3ffff2);
vpu_vcbus_set_mask(VDIN0_COM_GCLK_CTRL2, 0xf);
} else {
vpu_vcbus_clr_mask(VDIN0_COM_GCLK_CTRL, 0x3f3ffff0);
vpu_vcbus_clr_mask(VDIN0_COM_GCLK_CTRL2, 0xf);
}
break;
case VPU_VIU_VDIN1:
if (flag == VPU_CLK_GATE_ON) {
vpu_vcbus_set_mask(VDIN1_COM_GCLK_CTRL, 0x3f3ffff2);
vpu_vcbus_set_mask(VDIN1_COM_GCLK_CTRL2, 0xf);
} else {
vpu_vcbus_clr_mask(VDIN1_COM_GCLK_CTRL, 0x3f3ffff0);
vpu_vcbus_clr_mask(VDIN1_COM_GCLK_CTRL2, 0xf);
}
break;
case VPU_DI:
if (flag == VPU_CLK_GATE_ON) {
vpu_vcbus_set_mask(DI_CLKG_CTRL, 0x1d1e0003);
if ((vpu_chip_type == VPU_CHIP_GXTVBB) ||
(vpu_chip_type == VPU_CHIP_GXL) ||
(vpu_chip_type == VPU_CHIP_GXM) ||
(vpu_chip_type == VPU_CHIP_TXL)) {
vpu_vcbus_set_mask(DI_CLKG_CTRL, 0x60200000);
}
} else {
vpu_vcbus_clr_mask(DI_CLKG_CTRL, 0x1d1e0003);
if ((vpu_chip_type == VPU_CHIP_GXTVBB) ||
(vpu_chip_type == VPU_CHIP_GXL) ||
(vpu_chip_type == VPU_CHIP_GXM) ||
(vpu_chip_type == VPU_CHIP_TXL)) {
vpu_vcbus_clr_mask(DI_CLKG_CTRL, 0x60200000);
}
}
break;
case VPU_VPP:
if (flag == VPU_CLK_GATE_ON) {
vpu_vcbus_set_mask(VPP_GCLK_CTRL0, 0xffff3fcc);
if ((vpu_chip_type == VPU_CHIP_GXTVBB) ||
(vpu_chip_type == VPU_CHIP_GXL) ||
(vpu_chip_type == VPU_CHIP_GXM) ||
(vpu_chip_type == VPU_CHIP_TXL)) {
vpu_vcbus_set_mask(VPP_GCLK_CTRL0, 0xc030);
}
vpu_vcbus_set_mask(VPP_GCLK_CTRL1, 0xfff);
vpu_vcbus_set_mask(VPP_SC_GCLK_CTRL, 0x03fc0ffc);
vpu_vcbus_set_mask(VPP_XVYCC_GCLK_CTRL, 0x3ffff);
} else {
vpu_vcbus_clr_mask(VPP_GCLK_CTRL0, 0xffff3fcc);
if ((vpu_chip_type == VPU_CHIP_GXTVBB) ||
(vpu_chip_type == VPU_CHIP_GXL) ||
(vpu_chip_type == VPU_CHIP_GXM) ||
(vpu_chip_type == VPU_CHIP_TXL)) {
vpu_vcbus_clr_mask(VPP_GCLK_CTRL0, 0xc030);
}
vpu_vcbus_clr_mask(VPP_GCLK_CTRL1, 0xfff);
vpu_vcbus_clr_mask(VPP_SC_GCLK_CTRL, 0x03fc0ffc);
vpu_vcbus_clr_mask(VPP_XVYCC_GCLK_CTRL, 0x3ffff);
}
break;
default:
VPUPR("switch_vpu_clk_gate: unsupport vpu mod\n");
break;
}
spin_unlock_irqrestore(&vpu_clk_gate_lock, flags);
if (vpu_debug_print_flag) {
VPUPR("switch_vpu_clk_gate: %s %s\n",
vpu_mod_table[vmod],
((flag == VPU_CLK_GATE_ON) ? "ON" : "OFF"));
dump_stack();
}
}
/* *********************************************** */
void vpu_ctrl_probe(void)
{
spin_lock_init(&vpu_mem_lock);
spin_lock_init(&vpu_clk_gate_lock);
}

335
drivers/amlogic/media/common/vpu/vpu_ctrl.h Normal file
View File

@@ -0,0 +1,335 @@
/*
* drivers/amlogic/media/common/vpu/vpu_ctrl.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef __VPU_CTRL_H__
#define __VPU_CTRL_H__
#include <linux/amlogic/media/vpu/vpu.h>
#include "vpu.h"
/* #define LIMIT_VPU_CLK_LOW */
#define VPU_REG_END 0xffff
/* ************************************************ */
/* VPU frequency table, important. DO NOT modify!! */
/* ************************************************ */
#define CLK_FPLL_FREQ 2000 /* MHz */
/* GXBB */
/* freq max=666M, default=666M */
#define CLK_LEVEL_DFT_GXBB 7
#define CLK_LEVEL_MAX_GXBB 8
/* GXTVBB */
/* freq max=666M, default=666M */
#define CLK_LEVEL_DFT_GXTVBB 7
#define CLK_LEVEL_MAX_GXTVBB 8
/* GXL */
/* freq max=666M, default=666M */
#define CLK_LEVEL_DFT_GXL 7
#define CLK_LEVEL_MAX_GXL 8
/* GXM */
/* freq max=666M, default=666M */
#define CLK_LEVEL_DFT_GXM 7
#define CLK_LEVEL_MAX_GXM 8
/* TXLX */
/* freq max=666M, default=666M */
#define CLK_LEVEL_DFT_TXLX 7
#define CLK_LEVEL_MAX_TXLX 8
/* AXG */
/* freq max=250M, default=250M */
#define CLK_LEVEL_DFT_AXG 3
#define CLK_LEVEL_MAX_AXG 4
/* vpu clk setting */
enum vpu_mux_e {
FCLK_DIV4 = 0,
FCLK_DIV3,
FCLK_DIV5,
FCLK_DIV7,
MPLL_CLK1,
VID_PLL_CLK,
VID2_PLL_CLK,
GPLL_CLK,
};
static unsigned int fclk_div_table[] = {
4, /* mux 0 */
3, /* mux 1 */
5, /* mux 2 */
7, /* mux 3 */
2, /* invalid */
};
static unsigned int vpu_clk_table[10][3] = {
/* frequency clk_mux div */
{100000000, FCLK_DIV5, 3}, /* 0 */
{166666667, FCLK_DIV3, 3}, /* 1 */
{200000000, FCLK_DIV5, 1}, /* 2 */
{250000000, FCLK_DIV4, 1}, /* 3 */
{333333333, FCLK_DIV3, 1}, /* 4 */
{400000000, FCLK_DIV5, 0}, /* 5 */
{500000000, FCLK_DIV4, 0}, /* 6 */
{666666667, FCLK_DIV3, 0}, /* 7 */
{696000000, GPLL_CLK, 0}, /* 8 */
{850000000, GPLL_CLK, 0}, /* 9 */ /* invalid */
};
/* ************************************************ */
/* ******************************************************* */
/* VPU memory power down table */
/* ******************************************************* */
static struct vpu_ctrl_s vpu_mem_pd_gxb[] = {
/* vpu module, reg, bit, len */
{VPU_VIU_OSD1, HHI_VPU_MEM_PD_REG0, 0, 2},
{VPU_VIU_OSD2, HHI_VPU_MEM_PD_REG0, 2, 2},
{VPU_VIU_VD1, HHI_VPU_MEM_PD_REG0, 4, 2},
{VPU_VIU_VD2, HHI_VPU_MEM_PD_REG0, 6, 2},
{VPU_VIU_CHROMA, HHI_VPU_MEM_PD_REG0, 8, 2},
{VPU_VIU_OFIFO, HHI_VPU_MEM_PD_REG0, 10, 2},
{VPU_VIU_SCALE, HHI_VPU_MEM_PD_REG0, 12, 2},
{VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0, 14, 2},
{VPU_VIU_VDIN0, HHI_VPU_MEM_PD_REG0, 16, 2},
{VPU_VIU_VDIN1, HHI_VPU_MEM_PD_REG0, 18, 2},
{VPU_VIU_SRSCL, HHI_VPU_MEM_PD_REG0, 20, 2},
{VPU_VIU_OSDSR, HHI_VPU_MEM_PD_REG0, 22, 2},
{VPU_DI_PRE, HHI_VPU_MEM_PD_REG0, 26, 2},
{VPU_DI_POST, HHI_VPU_MEM_PD_REG0, 28, 2},
{VPU_SHARP, HHI_VPU_MEM_PD_REG0, 30, 2},
{VPU_VPU_ARB, HHI_VPU_MEM_PD_REG1, 14, 2},
{VPU_AFBC_DEC, HHI_VPU_MEM_PD_REG1, 16, 2},
{VPU_VENCP, HHI_VPU_MEM_PD_REG1, 20, 2},
{VPU_VENCL, HHI_VPU_MEM_PD_REG1, 22, 2},
{VPU_VENCI, HHI_VPU_MEM_PD_REG1, 24, 2},
{VPU_MOD_MAX, VPU_REG_END, 0, 0},
};
static struct vpu_ctrl_s vpu_mem_pd_gxtvbb[] = {
/* vpu module, reg, bit, len */
{VPU_VIU_OSD1, HHI_VPU_MEM_PD_REG0, 0, 2},
{VPU_VIU_OSD2, HHI_VPU_MEM_PD_REG0, 2, 2},
{VPU_VIU_VD1, HHI_VPU_MEM_PD_REG0, 4, 2},
{VPU_VIU_VD2, HHI_VPU_MEM_PD_REG0, 6, 2},
{VPU_VIU_CHROMA, HHI_VPU_MEM_PD_REG0, 8, 2},
{VPU_VIU_OFIFO, HHI_VPU_MEM_PD_REG0, 10, 2},
{VPU_VIU_SCALE, HHI_VPU_MEM_PD_REG0, 12, 2},
{VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0, 14, 2},
{VPU_VIU_VDIN0, HHI_VPU_MEM_PD_REG0, 16, 2},
{VPU_VIU_VDIN1, HHI_VPU_MEM_PD_REG0, 18, 2},
{VPU_VIU_SRSCL, HHI_VPU_MEM_PD_REG0, 20, 2},
{VPU_AFBC_DEC1, HHI_VPU_MEM_PD_REG0, 22, 2},
{VPU_DI_PRE, HHI_VPU_MEM_PD_REG0, 26, 2},
{VPU_DI_POST, HHI_VPU_MEM_PD_REG0, 28, 2},
{VPU_SHARP, HHI_VPU_MEM_PD_REG0, 30, 2},
{VPU_VPU_ARB, HHI_VPU_MEM_PD_REG1, 14, 2},
{VPU_AFBC_DEC, HHI_VPU_MEM_PD_REG1, 16, 2},
{VPU_VENCP, HHI_VPU_MEM_PD_REG1, 20, 2},
{VPU_VENCL, HHI_VPU_MEM_PD_REG1, 22, 2},
{VPU_VENCI, HHI_VPU_MEM_PD_REG1, 24, 2},
{VPU_LDIM_STTS, HHI_VPU_MEM_PD_REG1, 28, 2},
{VPU_XVYCC_LUT, HHI_VPU_MEM_PD_REG1, 30, 2},
{VPU_MOD_MAX, VPU_REG_END, 0, 0},
};
static struct vpu_ctrl_s vpu_mem_pd_gxl[] = {
/* vpu module, reg, bit, len */
{VPU_VIU_OSD1, HHI_VPU_MEM_PD_REG0, 0, 2},
{VPU_VIU_OSD2, HHI_VPU_MEM_PD_REG0, 2, 2},
{VPU_VIU_VD1, HHI_VPU_MEM_PD_REG0, 4, 2},
{VPU_VIU_VD2, HHI_VPU_MEM_PD_REG0, 6, 2},
{VPU_VIU_CHROMA, HHI_VPU_MEM_PD_REG0, 8, 2},
{VPU_VIU_OFIFO, HHI_VPU_MEM_PD_REG0, 10, 2},
{VPU_VIU_SCALE, HHI_VPU_MEM_PD_REG0, 12, 2},
{VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0, 14, 2},
{VPU_VIU_VDIN0, HHI_VPU_MEM_PD_REG0, 16, 2},
{VPU_VIU_VDIN1, HHI_VPU_MEM_PD_REG0, 18, 2},
{VPU_DI_PRE, HHI_VPU_MEM_PD_REG0, 26, 2},
{VPU_DI_POST, HHI_VPU_MEM_PD_REG0, 28, 2},
{VPU_SHARP, HHI_VPU_MEM_PD_REG0, 30, 2},
{VPU_VPU_ARB, HHI_VPU_MEM_PD_REG1, 14, 2},
{VPU_AFBC_DEC, HHI_VPU_MEM_PD_REG1, 16, 2},
{VPU_VENCP, HHI_VPU_MEM_PD_REG1, 20, 2},
{VPU_VENCL, HHI_VPU_MEM_PD_REG1, 22, 2},
{VPU_VENCI, HHI_VPU_MEM_PD_REG1, 24, 2},
{VPU_VIU1_WM, HHI_VPU_MEM_PD_REG2, 0, 2},
{VPU_MOD_MAX, VPU_REG_END, 0, 0},
};
static struct vpu_ctrl_s vpu_mem_pd_txlx[] = {
/* vpu module, reg, bit, len */
{VPU_VIU_OSD1, HHI_VPU_MEM_PD_REG0, 0, 2},
{VPU_VIU_OSD2, HHI_VPU_MEM_PD_REG0, 2, 2},
{VPU_VIU_VD1, HHI_VPU_MEM_PD_REG0, 4, 2},
{VPU_VIU_VD2, HHI_VPU_MEM_PD_REG0, 6, 2},
{VPU_VIU_CHROMA, HHI_VPU_MEM_PD_REG0, 8, 2},
{VPU_VIU_OFIFO, HHI_VPU_MEM_PD_REG0, 10, 2},
{VPU_VIU_SCALE, HHI_VPU_MEM_PD_REG0, 12, 2},
{VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0, 14, 2},
{VPU_VIU_VDIN0, HHI_VPU_MEM_PD_REG0, 16, 2},
{VPU_VIU_VDIN1, HHI_VPU_MEM_PD_REG0, 18, 2},
{VPU_VIU_SRSCL, HHI_VPU_MEM_PD_REG0, 20, 2},
{VPU_AFBC_DEC1, HHI_VPU_MEM_PD_REG0, 22, 2},
{VPU_DI_PRE, HHI_VPU_MEM_PD_REG0, 26, 2},
{VPU_DI_POST, HHI_VPU_MEM_PD_REG0, 28, 2},
{VPU_SHARP, HHI_VPU_MEM_PD_REG0, 30, 2},
{VPU_VKSTONE, HHI_VPU_MEM_PD_REG1, 4, 2},
{VPU_DOLBY_CORE3, HHI_VPU_MEM_PD_REG1, 6, 2},
{VPU_DOLBY0, HHI_VPU_MEM_PD_REG1, 8, 2},
{VPU_DOLBY1A, HHI_VPU_MEM_PD_REG1, 10, 2},
{VPU_DOLBY1B, HHI_VPU_MEM_PD_REG1, 12, 2},
{VPU_VPU_ARB, HHI_VPU_MEM_PD_REG1, 14, 2},
{VPU_AFBC_DEC, HHI_VPU_MEM_PD_REG1, 16, 2},
{VPU_OSD_AFBCD, HHI_VPU_MEM_PD_REG1, 18, 2},
{VPU_VENCP, HHI_VPU_MEM_PD_REG1, 20, 2},
{VPU_VENCL, HHI_VPU_MEM_PD_REG1, 22, 2},
{VPU_VENCI, HHI_VPU_MEM_PD_REG1, 24, 2},
{VPU_LDIM_STTS, HHI_VPU_MEM_PD_REG1, 28, 2},
{VPU_XVYCC_LUT, HHI_VPU_MEM_PD_REG1, 30, 2},
{VPU_VIU1_WM, HHI_VPU_MEM_PD_REG2, 0, 2},
{VPU_MOD_MAX, VPU_REG_END, 0, 0},
};
static struct vpu_ctrl_s vpu_mem_pd_axg[] = {
/* vpu module, reg, bit, len */
{VPU_VIU_OSD1, HHI_VPU_MEM_PD_REG0, 0, 2},
{VPU_VIU_OFIFO, HHI_VPU_MEM_PD_REG0, 2, 2},
{VPU_VPU_ARB, HHI_VPU_MEM_PD_REG0, 4, 2},
{VPU_VENCL, HHI_VPU_MEM_PD_REG0, 6, 2},
{VPU_MOD_MAX, VPU_REG_END, 0, 0},
};
/* ******************************************************* */
/* VPU clock gate table */
/* ******************************************************* */
static struct vpu_ctrl_s vpu_clk_gate_gxb[] = {
/* vpu module, reg, bit, len */
{VPU_VPU_TOP, VPU_CLK_GATE, 1, 1}, /* vpu_system_clk */
{VPU_VPU_CLKB, VPU_CLK_GATE, 16, 1},
{VPU_RDMA, VPU_CLK_GATE, 15, 1}, /* rdma_clk */
{VPU_VLOCK, VPU_CLK_GATE, 14, 1},
{VPU_MISC, VPU_CLK_GATE, 6, 1}, /* hs,vs interrupt*/
{VPU_VENCP, VPU_CLK_GATE, 3, 1},
{VPU_VENCP, VPU_CLK_GATE, 0, 1},
{VPU_VENCL, VPU_CLK_GATE, 4, 2},
{VPU_VENCI, VPU_CLK_GATE, 10, 2},
{VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 24, 6},
{VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 4, 18},
{VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 1, 1},
{VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL2, 0, 4},
{VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 24, 6},
{VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 4, 18},
{VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 1, 1},
{VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL2, 0, 4},
{VPU_DI, DI_CLKG_CTRL, 26, 3},
{VPU_DI, DI_CLKG_CTRL, 24, 1},
{VPU_DI, DI_CLKG_CTRL, 17, 4},
{VPU_DI, DI_CLKG_CTRL, 0, 2},
{VPU_VPP, VPP_GCLK_CTRL0, 16, 16},
{VPU_VPP, VPP_GCLK_CTRL0, 6, 8},
{VPU_VPP, VPP_GCLK_CTRL0, 2, 2},
{VPU_VPP, VPP_GCLK_CTRL1, 0, 12},
{VPU_VPP, VPP_SC_GCLK_CTRL, 18, 8},
{VPU_VPP, VPP_SC_GCLK_CTRL, 2, 10},
{VPU_VPP, VPP_XVYCC_GCLK_CTRL, 0, 18},
{VPU_MAX, VPU_REG_END, 0, 0},
};
static struct vpu_ctrl_s vpu_clk_gate_gxl[] = {
/* vpu module, reg, bit, len */
{VPU_VPU_TOP, VPU_CLK_GATE, 1, 1}, /* vpu_system_clk */
{VPU_VPU_CLKB, VPU_CLK_GATE, 16, 2},
{VPU_RDMA, VPU_CLK_GATE, 15, 1}, /* rdma_clk */
{VPU_VLOCK, VPU_CLK_GATE, 14, 1},
{VPU_MISC, VPU_CLK_GATE, 6, 1}, /* hs,vs interrupt*/
{VPU_VENCP, VPU_CLK_GATE, 3, 1},
{VPU_VENCP, VPU_CLK_GATE, 0, 1},
{VPU_VENCL, VPU_CLK_GATE, 4, 2},
{VPU_VENCI, VPU_CLK_GATE, 10, 2},
{VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 24, 6},
{VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 4, 18},
{VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 1, 1},
{VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL2, 0, 4},
{VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 24, 6},
{VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 4, 18},
{VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 1, 1},
{VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL2, 0, 4},
{VPU_DI, DI_CLKG_CTRL, 26, 5},
{VPU_DI, DI_CLKG_CTRL, 24, 1},
{VPU_DI, DI_CLKG_CTRL, 17, 5},
{VPU_DI, DI_CLKG_CTRL, 0, 2},
{VPU_VPP, VPP_GCLK_CTRL0, 2, 30},
{VPU_VPP, VPP_GCLK_CTRL1, 0, 12},
{VPU_VPP, VPP_SC_GCLK_CTRL, 18, 8},
{VPU_VPP, VPP_SC_GCLK_CTRL, 2, 10},
{VPU_VPP, VPP_XVYCC_GCLK_CTRL, 0, 18},
{VPU_MAX, VPU_REG_END, 0, 0},
};
static struct vpu_ctrl_s vpu_clk_gate_txlx[] = {
/* vpu module, reg, bit, len */
{VPU_VPU_TOP, VPU_CLK_GATE, 1, 1}, /* vpu_system_clk */
{VPU_VPU_CLKB, VPU_CLK_GATE, 16, 1},
{VPU_RDMA, VPU_CLK_GATE, 15, 1}, /* rdma_clk */
{VPU_VLOCK, VPU_CLK_GATE, 14, 1},
{VPU_MISC, VPU_CLK_GATE, 6, 1}, /* hs,vs interrupt*/
{VPU_VENCP, VPU_CLK_GATE, 3, 1},
{VPU_VENCP, VPU_CLK_GATE, 0, 1},
{VPU_VENCL, VPU_CLK_GATE, 4, 2},
{VPU_VENCI, VPU_CLK_GATE, 10, 2},
{VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 24, 6},
{VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 4, 18},
{VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 1, 1},
{VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL2, 0, 4},
{VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 24, 6},
{VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 4, 18},
{VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 1, 1},
{VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL2, 0, 4},
{VPU_VPP, VPP_GCLK_CTRL0, 2, 30},
{VPU_VPP, VPP_GCLK_CTRL1, 0, 12},
{VPU_VPP, VPP_SC_GCLK_CTRL, 18, 8},
{VPU_VPP, VPP_SC_GCLK_CTRL, 2, 10},
{VPU_VPP, VPP_XVYCC_GCLK_CTRL, 0, 18},
{VPU_MAX, VPU_REG_END, 0, 0},
};
static struct vpu_ctrl_s vpu_clk_gate_axg[] = {
/* vpu module, reg, bit, len */
{VPU_VPU_TOP, VPU_CLK_GATE, 1, 1},
{VPU_VLOCK, VPU_CLK_GATE, 14, 1},
{VPU_MISC, VPU_CLK_GATE, 6, 1},
{VPU_VENCL, VPU_CLK_GATE, 4, 2},
{VPU_VPP, VPP_GCLK_CTRL0, 16, 16},
{VPU_VPP, VPP_GCLK_CTRL0, 6, 8},
{VPU_VPP, VPP_GCLK_CTRL0, 2, 2},
{VPU_VPP, VPP_GCLK_CTRL1, 0, 12},
{VPU_VPP, VPP_SC_GCLK_CTRL, 18, 8},
{VPU_VPP, VPP_SC_GCLK_CTRL, 2, 10},
{VPU_VPP, VPP_XVYCC_GCLK_CTRL, 0, 18},
{VPU_MAX, VPU_REG_END, 0, 0},
};
/* ************************************************ */
#endif

26
drivers/amlogic/media/common/vpu/vpu_module.h
View File

@@ -32,41 +32,36 @@ static char *vpu_mod_table[] = {
"viu_osd_scaler",
"viu_vdin0",
"viu_vdin1",
"pic_rot1",
"pic_rot2",
"pic_rot3",
"viu_super_scaler",
"viu_osd_super_scaler",
"afbc_dec",
"afbc_dec1",
"di_pre",
"di_post",
"viu_sharpness_line_buffer",
"viu2_osd1",
"viu2_osd2",
"d2d3",
"viu2_vd1",
"viu2_chroma",
"viu2_ofifo",
"viu2_scaler",
"viu2_osd_scaler",
"vdin_arbitor_am_async",
"vkstone",
"dolby_core3",
"dolby0",
"dolby_1a",
"dolby_1b",
"vpu_arb",
"display_arbitor_am_async",
"osd1_afbcd",
"afbc_dec0",
"afbc_dec",
"vpu_arbitor2_am_async",
"osd_afbcd",
"vencp",
"vencl",
"venci",
"isp",
"cvd2",
"atv_dmd",
"ldim_stts",
"xvycc_lut",
"viu1_water_mark",
"vpu_mod_max",
/* for clk_gate */
"vpu_top",
@@ -79,6 +74,11 @@ static char *vpu_mod_table[] = {
"vpp",
"none",
"none",
"none",
"none",
"none",
"none",
};
#endif

162
drivers/amlogic/media/common/vpu/vpu_reg.c
View File

@@ -21,7 +21,7 @@
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/amlogic/cpu_version.h>
#include <linux/amlogic/iomap.h>
#include "vpu_reg.h"
#include "vpu.h"
@@ -30,156 +30,14 @@
* *********************************
*/
#define VPU_MAP_HIUBUS 0
#define VPU_MAP_VCBUS 1
struct reg_map_s {
unsigned int base_addr;
unsigned int size;
void __iomem *p;
int flag;
};
static struct reg_map_s *vpu_map;
static int vpu_map_num;
static struct reg_map_s vpu_reg_maps_gx[] = {
{ /* HIU */
.base_addr = 0xc883c000,
.size = 0x400,
},
{ /* VCBUS */
.base_addr = 0xd0100000,
.size = 0xa000,
},
};
static struct reg_map_s vpu_reg_maps_axg[] = {
{ /* HIU */
.base_addr = 0xff63c000,
.size = 0x400,
},
{ /* VCBUS */
.base_addr = 0xff900000,
.size = 0xa000,
},
};
int vpu_ioremap(void)
{
int i;
int ret = 0;
switch (vpu_chip_type) {
case VPU_CHIP_GXBB:
case VPU_CHIP_GXTVBB:
case VPU_CHIP_GXL:
case VPU_CHIP_GXM:
case VPU_CHIP_TXL:
vpu_map = vpu_reg_maps_gx;
vpu_map_num = ARRAY_SIZE(vpu_reg_maps_gx);
break;
case VPU_CHIP_AXG:
vpu_map = vpu_reg_maps_axg;
vpu_map_num = ARRAY_SIZE(vpu_reg_maps_axg);
break;
default:
vpu_map = NULL;
vpu_map_num = 0;
VPUERR("%s: invalid chip type\n", __func__);
break;
}
for (i = 0; i < vpu_map_num; i++) {
vpu_map[i].p = ioremap(vpu_map[i].base_addr, vpu_map[i].size);
if (vpu_map[i].p == NULL) {
vpu_map[i].flag = 0;
VPUERR("VPU reg map failed: 0x%x\n",
vpu_map[i].base_addr);
ret = -1;
} else {
vpu_map[i].flag = 1;
#if 0
VPUPR("VPU reg mapped: 0x%x -> %p\n",
vpu_map[i].base_addr, vpu_map[i].p);
#endif
}
}
return ret;
}
static int vpu_ioremap_check(int n)
{
if (vpu_map == NULL)
return -1;
if (n >= vpu_map_num)
return -1;
if (vpu_map[n].flag == 0) {
VPUERR("reg 0x%x mapped error\n", vpu_map[n].base_addr);
return -1;
}
return 0;
}
static void __iomem *vpu_hiu_reg_check(unsigned int _reg)
{
void __iomem *p = NULL;
int reg_bus;
unsigned int reg_offset;
reg_bus = VPU_MAP_HIUBUS;
if (vpu_ioremap_check(reg_bus))
return NULL;
reg_offset = REG_OFFSET_HIU(_reg);
if (reg_offset > vpu_map[reg_bus].size) {
VPUERR("invalid reg offset: 0x%02x\n", _reg);
return NULL;
}
p = vpu_map[reg_bus].p + reg_offset;
return p;
}
static void __iomem *vpu_vcbus_reg_check(unsigned int _reg)
{
void __iomem *p = NULL;
int reg_bus;
unsigned int reg_offset;
reg_bus = VPU_MAP_VCBUS;
if (vpu_ioremap_check(reg_bus))
return NULL;
reg_offset = REG_OFFSET_VCBUS(_reg);
if (reg_offset > vpu_map[reg_bus].size) {
VPUERR("invalid reg offset: 0x%04x\n", _reg);
return NULL;
}
p = vpu_map[reg_bus].p + reg_offset;
return p;
}
unsigned int vpu_hiu_read(unsigned int _reg)
{
void __iomem *p;
p = vpu_hiu_reg_check(_reg);
if (p)
return readl(p);
else
return 0;
return aml_read_hiubus(_reg);
};
void vpu_hiu_write(unsigned int _reg, unsigned int _value)
{
void __iomem *p;
p = vpu_hiu_reg_check(_reg);
if (p)
writel(_value, p);
aml_write_hiubus(_reg, _value);
};
void vpu_hiu_setb(unsigned int _reg, unsigned int _value,
@@ -208,22 +66,12 @@ void vpu_hiu_clr_mask(unsigned int _reg, unsigned int _mask)
unsigned int vpu_vcbus_read(unsigned int _reg)
{
void __iomem *p;
p = vpu_vcbus_reg_check(_reg);
if (p)
return readl(p);
else
return 0;
return aml_read_vcbus(_reg);
};
void vpu_vcbus_write(unsigned int _reg, unsigned int _value)
{
void __iomem *p;
p = vpu_vcbus_reg_check(_reg);
if (p)
writel(_value, p);
aml_write_vcbus(_reg, _value);
};
void vpu_vcbus_setb(unsigned int _reg, unsigned int _value,

15
drivers/amlogic/media/common/vpu/vpu_reg.h
View File

@@ -27,22 +27,7 @@
* register define
* *********************************
*/
/* base & offset */
#define REG_BASE_AOBUS (0xc8100000L)
#define REG_BASE_CBUS (0xc1100000L)
#define REG_BASE_HIU (0xc883c000L)
#define REG_BASE_VCBUS (0xd0100000L)
#define REG_OFFSET_AOBUS(reg) ((reg))
#define REG_OFFSET_CBUS(reg) ((reg << 2))
#define REG_OFFSET_HIU(reg) (((reg & 0xff) << 2))
#define REG_OFFSET_VCBUS(reg) ((reg << 2))
/* memory mapping */
#define REG_ADDR_AOBUS(reg) (REG_BASE_AOBUS + REG_OFFSET_AOBUS(reg))
#define REG_ADDR_CBUS(reg) (REG_BASE_CBUS + REG_OFFSET_CBUS(reg))
#define REG_ADDR_HIU(reg) (REG_BASE_HIU + REG_OFFSET_HIU(reg))
#define REG_ADDR_VCBUS(reg) (REG_BASE_VCBUS + REG_OFFSET_VCBUS(reg))
/* offset address */
#define AO_RTI_GEN_PWR_SLEEP0 ((0x00 << 10) | (0x3a << 2))
/* HHI bus */

40
include/linux/amlogic/media/vpu/vpu.h
View File

@@ -18,6 +18,9 @@
#ifndef __VPU_H__
#define __VPU_H__
/* ************************************************ */
/* VPU module define */
/* ************************************************ */
enum vpu_mod_e {
VPU_VIU_OSD1 = 0, /* reg0[1:0] //common */
VPU_VIU_OSD2, /* reg0[3:2] //common */
@@ -29,41 +32,36 @@ enum vpu_mod_e {
VPU_VIU_OSD_SCALE, /* reg0[15:14] //common */
VPU_VIU_VDIN0, /* reg0[17:16] //common */
VPU_VIU_VDIN1, /* reg0[19:18] //common */
VPU_PIC_ROT1, /* reg0[21:20] */
VPU_PIC_ROT2, /* reg0[23:22] */
VPU_PIC_ROT3, /* reg0[25:24] */
VPU_VIU_SRSCL, /* reg0[21:20] //G9TV, GXBB, GXTVBB */
VPU_VIU_OSDSR, /* reg0[23:22] //G9TV, GXBB */
VPU_AFBC_DEC1, /* reg0[23:22] //GXTVBB */
VPU_VIU_SRSCL, /* reg0[21:20] //GXBB, GXTVBB, TXLX */
VPU_VIU_OSDSR, /* reg0[23:22] //GXBB */
VPU_AFBC_DEC1, /* reg0[23:22] //GXTVBB, TXLX */
VPU_DI_PRE, /* reg0[27:26] //common */
VPU_DI_POST, /* reg0[29:28] //common */
VPU_SHARP, /* reg0[31:30] //common */
VPU_SHARP, /* reg0[31:30] //common */
VPU_VIU2_OSD1, /* reg1[1:0] */
VPU_VIU2_OSD2, /* reg1[3:2] */
VPU_D2D3, /* reg1[3:0] //G9TV */
VPU_VIU2_VD1, /* reg1[5:4] */
VPU_VIU2_CHROMA, /* reg1[7:6] */
VPU_VIU2_OFIFO, /* reg1[9:8] */
VPU_VIU2_SCALE, /* reg1[11:10] */
VPU_VIU2_OSD_SCALE, /* reg1[13:12] */
VPU_VDIN_AM_ASYNC, /* reg1[15:14] //G9TV */
VPU_VPU_ARB, /* reg1[15:14] //GXBB, GXTVBB, GXL */
VPU_VDISP_AM_ASYNC, /* reg1[17:16] //G9TV */
VPU_OSD1_AFBCD, /* reg1[17:16] //GXTVBB */
VPU_AFBC_DEC0, /* reg1[17:16] //GXTVBB */
VPU_AFBC_DEC, /* reg1[17:16] //GXBB */
VPU_VPUARB2_AM_ASYNC, /* reg1[19:18] //G9TV */
VPU_VKSTONE, /* reg1[5:4] //TXLX */
VPU_DOLBY_CORE3, /* reg1[7:6] //TXLX */
VPU_DOLBY0, /* reg1[9:8] //TXLX */
VPU_DOLBY1A, /* reg1[11:10] //TXLX */
VPU_DOLBY1B, /* reg1[13:12] //TXLX */
VPU_VPU_ARB, /* reg1[15:14] //GXBB, GXTVBB, GXL, TXLX */
VPU_AFBC_DEC, /* reg1[17:16] //GXBB, GXTVBB, TXL, TXLX */
VPU_OSD_AFBCD, /* reg1[19:18] //TXLX */
VPU_VENCP, /* reg1[21:20] //common */
VPU_VENCL, /* reg1[23:22] //common */
VPU_VENCI, /* reg1[25:24] //common */
VPU_ISP, /* reg1[27:26] */
VPU_CVD2, /* reg1[29:28] //G9TV, G9BB */
VPU_ATV_DMD, /* reg1[31:30] //G9TV, G9BB */
VPU_LDIM_STTS, /* reg1[29:28] //GXTVBB, GXL */
VPU_XVYCC_LUT, /* reg1[31:30] //GXTVBB, GXL */
VPU_LDIM_STTS, /* reg1[29:28] //GXTVBB, GXL, TXL, TXLX */
VPU_XVYCC_LUT, /* reg1[31:30] //GXTVBB, GXL, TXL, TXLX */
VPU_VIU1_WM, /* reg2[1:0] //GXL, TXL */
VPU_VIU1_WM, /* reg2[1:0] //GXL, TXL, TXLX */
VPU_MOD_MAX,
/* for clk_gate */
VPU_VPU_TOP,