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amvecm: add hdr support for g12a

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PD#156734: amvecm: add hdr support for g12a

Change-Id: Ia1f5d3d7b13a6cec7f07bfe6cb7d06264ffcc82d
Signed-off-by: MingLiang Dong <mingliang.dong@amlogic.com>
This commit is contained in:
MingLiang Dong
2018-02-08 19:57:25 +08:00
committed by Yixun Lan
parent e65794797d
commit 9635c511bf
6 changed files with 1620 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/amlogic/media/enhancement/amvecm/Makefile
View File

@@ -4,5 +4,5 @@
ccflags-y := -I$(PWD)/$(src)/dolby_vision/
obj-$(CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM) += am_vecm.o
am_vecm-objs := amve.o amcm.o amcsc.o amvecm.o amdolby_vision.o keystone_correction.o bitdepth.o
am_vecm-objs := amve.o amcm.o amcsc.o amvecm.o amdolby_vision.o keystone_correction.o bitdepth.o set_hdr2_v0.o

51
drivers/amlogic/media/enhancement/amvecm/amcsc.c
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@@ -34,6 +34,8 @@
#include "../../osd/osd_rdma.h"
#include "amcsc.h"
#include "set_hdr2_v0.h"
#define pr_csc(fmt, args...)\
do {\
@@ -198,6 +200,11 @@ static uint force_csc_type = 0xff;
module_param(force_csc_type, uint, 0664);
MODULE_PARM_DESC(force_csc_type, "\n force colour space convert type\n");
static uint fresh_vs;
module_param(fresh_vs, uint, 0664);
MODULE_PARM_DESC(fresh_vs, "\n fresh_vs\n");
static uint cur_hdr_support;
module_param(cur_hdr_support, uint, 0664);
MODULE_PARM_DESC(cur_hdr_support, "\n cur_hdr_support\n");
@@ -2997,7 +3004,7 @@ int signal_type_changed(struct vframe_s *vf, struct vinfo_s *vinfo)
}
if (cur_knee_factor != knee_factor) {
pr_csc("Knee factor changed.\n");
change_flag |= SIG_KNEE_FACTOR;
//change_flag |= SIG_KNEE_FACTOR;
}
if (cur_hdr_process_mode != hdr_process_mode) {
pr_csc("HDR mode changed.\n");
@@ -4804,6 +4811,12 @@ static int vpp_matrix_update(
if (vf && vinfo)
signal_change_flag = signal_type_changed(vf, vinfo);
if ((!signal_change_flag) && (force_csc_type == 0xff) && (!fresh_vs))
return 0;
if (fresh_vs > 0)
fresh_vs = 0;
if (force_csc_type != 0xff)
csc_type = force_csc_type;
else
@@ -4910,23 +4923,43 @@ static int vpp_matrix_update(
if (get_hdr_type() & HLG_FLAG)
need_adjust_contrast_saturation =
hlg_process(csc_type, vinfo, p);
else
need_adjust_contrast_saturation =
hdr_process(csc_type, vinfo, p);
else {
if (get_cpu_type() ==
MESON_CPU_MAJOR_ID_G12A) {
hdr2sdr_func(VD1_HDR);
hdrbypass_func(OSD1_HDR);
} else
need_adjust_contrast_saturation
= hdr_process(csc_type,
vinfo, p);
}
}
} else {
if ((csc_type < VPP_MATRIX_BT2020YUV_BT2020RGB) &&
sdr_process_mode)
sdr_process_mode) {
/* for gxl and gxm SDR to HDR process */
sdr_hdr_process(csc_type, vinfo, p);
else {
if (get_cpu_type() ==
MESON_CPU_MAJOR_ID_G12A) {
sdr2hdr_func(VD1_HDR);
sdr2hdr_func(OSD1_HDR);
} else
sdr_hdr_process(csc_type,
vinfo, p);
} else {
/* for gxtvbb and gxl HDR bypass process */
if ((get_hdr_type() & HLG_FLAG) &&
(vinfo->viu_color_fmt !=
COLOR_FMT_RGB444))
bypass_hlg_process(csc_type, vinfo, p);
else
bypass_hdr_process(csc_type, vinfo, p);
else {
if (get_cpu_type() ==
MESON_CPU_MAJOR_ID_G12A) {
hdrbypass_func(VD1_HDR);
hdrbypass_func(OSD1_HDR);
} else
bypass_hdr_process(csc_type,
vinfo, p);
}
}
}
if (cur_hdr_process_mode != hdr_process_mode) {

2
drivers/amlogic/media/enhancement/amvecm/amvecm.c
View File

@@ -4276,7 +4276,7 @@ static int aml_vecm_probe(struct platform_device *pdev)
aml_vecm_dt_parse(pdev);
if (is_meson_gxm_cpu())
dolby_vision_init_receiver();
probe_ok = 0;/*temp mark for g12a bringup*/
probe_ok = 1;
pr_info("%s: ok\n", __func__);
return 0;

121
drivers/amlogic/media/enhancement/amvecm/arch/vpp_hdr_regs.h
View File

@@ -36,4 +36,125 @@ extern struct am_regs_s r_lut_hdr_sdr_level1;
extern struct am_regs_s r_lut_hdr_sdr_level2;
extern struct am_regs_s r_lut_hdr_sdr_level3;
#define VD1_HDR2_CTRL 0x3800
#define VD1_HDR2_CLK_GATE 0x3801
#define VD1_HDR2_MATRIXI_COEF00_01 0x3802
#define VD1_HDR2_MATRIXI_COEF02_10 0x3803
#define VD1_HDR2_MATRIXI_COEF11_12 0x3804
#define VD1_HDR2_MATRIXI_COEF20_21 0x3805
#define VD1_HDR2_MATRIXI_COEF22 0x3806
#define VD1_HDR2_MATRIXI_COEF30_31 0x3807
#define VD1_HDR2_MATRIXI_COEF32_40 0x3808
#define VD1_HDR2_MATRIXI_COEF41_42 0x3809
#define VD1_HDR2_MATRIXI_OFFSET0_1 0x380a
#define VD1_HDR2_MATRIXI_OFFSET2 0x380b
#define VD1_HDR2_MATRIXI_PRE_OFFSET0_1 0x380c
#define VD1_HDR2_MATRIXI_PRE_OFFSET2 0x380d
#define VD1_HDR2_MATRIXO_COEF00_01 0x380e
#define VD1_HDR2_MATRIXO_COEF02_10 0x380f
#define VD1_HDR2_MATRIXO_COEF11_12 0x3810
#define VD1_HDR2_MATRIXO_COEF20_21 0x3811
#define VD1_HDR2_MATRIXO_COEF22 0x3812
#define VD1_HDR2_MATRIXO_COEF30_31 0x3813
#define VD1_HDR2_MATRIXO_COEF32_40 0x3814
#define VD1_HDR2_MATRIXO_COEF41_42 0x3815
#define VD1_HDR2_MATRIXO_OFFSET0_1 0x3816
#define VD1_HDR2_MATRIXO_OFFSET2 0x3817
#define VD1_HDR2_MATRIXO_PRE_OFFSET0_1 0x3818
#define VD1_HDR2_MATRIXO_PRE_OFFSET2 0x3819
#define VD1_HDR2_MATRIXI_CLIP 0x381a
#define VD1_HDR2_MATRIXO_CLIP 0x381b
#define VD1_HDR2_CGAIN_OFFT 0x381c
#define VD1_EOTF_LUT_ADDR_PORT 0x381e
#define VD1_EOTF_LUT_DATA_PORT 0x381f
#define VD1_OETF_LUT_ADDR_PORT 0x3820
#define VD1_OETF_LUT_DATA_PORT 0x3821
#define VD1_CGAIN_LUT_ADDR_PORT 0x3822
#define VD1_CGAIN_LUT_DATA_PORT 0x3823
#define VD1_HDR2_CGAIN_COEF0 0x3824
#define VD1_HDR2_CGAIN_COEF1 0x3825
#define VD1_OGAIN_LUT_ADDR_PORT 0x3826
#define VD1_OGAIN_LUT_DATA_PORT 0x3827
#define VD1_HDR2_ADPS_CTRL 0x3828
#define VD1_HDR2_ADPS_ALPHA0 0x3829
#define VD1_HDR2_ADPS_ALPHA1 0x382a
#define VD1_HDR2_ADPS_BETA0 0x382b
#define VD1_HDR2_ADPS_BETA1 0x382c
#define VD1_HDR2_ADPS_BETA2 0x382d
#define VD1_HDR2_ADPS_COEF0 0x382e
#define VD1_HDR2_ADPS_COEF1 0x382f
#define VD1_HDR2_GMUT_CTRL 0x3830
#define VD1_HDR2_GMUT_COEF0 0x3831
#define VD1_HDR2_GMUT_COEF1 0x3832
#define VD1_HDR2_GMUT_COEF2 0x3833
#define VD1_HDR2_GMUT_COEF3 0x3834
#define VD1_HDR2_GMUT_COEF4 0x3835
#define VD1_HDR2_PIPE_CTRL1 0x3836
#define VD1_HDR2_PIPE_CTRL2 0x3837
#define VD1_HDR2_PIPE_CTRL3 0x3838
#define VD1_HDR2_PROC_WIN1 0x3839
#define VD1_HDR2_PROC_WIN2 0x383a
#define VD1_HDR2_MATRIXI_EN_CTRL 0x383b
#define VD1_HDR2_MATRIXO_EN_CTRL 0x383c
#define OSD1_HDR2_CTRL 0x38a0
#define OSD1_HDR2_CLK_GATE 0x38a1
#define OSD1_HDR2_MATRIXI_COEF00_01 0x38a2
#define OSD1_HDR2_MATRIXI_COEF02_10 0x38a3
#define OSD1_HDR2_MATRIXI_COEF11_12 0x38a4
#define OSD1_HDR2_MATRIXI_COEF20_21 0x38a5
#define OSD1_HDR2_MATRIXI_COEF22 0x38a6
#define OSD1_HDR2_MATRIXI_COEF30_31 0x38a7
#define OSD1_HDR2_MATRIXI_COEF32_40 0x38a8
#define OSD1_HDR2_MATRIXI_COEF41_42 0x38a9
#define OSD1_HDR2_MATRIXI_OFFSET0_1 0x38aa
#define OSD1_HDR2_MATRIXI_OFFSET2 0x38ab
#define OSD1_HDR2_MATRIXI_PRE_OFFSET0_1 0x38ac
#define OSD1_HDR2_MATRIXI_PRE_OFFSET2 0x38ad
#define OSD1_HDR2_MATRIXO_COEF00_01 0x38ae
#define OSD1_HDR2_MATRIXO_COEF02_10 0x38af
#define OSD1_HDR2_MATRIXO_COEF11_12 0x38b0
#define OSD1_HDR2_MATRIXO_COEF20_21 0x38b1
#define OSD1_HDR2_MATRIXO_COEF22 0x38b2
#define OSD1_HDR2_MATRIXO_COEF30_31 0x38b3
#define OSD1_HDR2_MATRIXO_COEF32_40 0x38b4
#define OSD1_HDR2_MATRIXO_COEF41_42 0x38b5
#define OSD1_HDR2_MATRIXO_OFFSET0_1 0x38b6
#define OSD1_HDR2_MATRIXO_OFFSET2 0x38b7
#define OSD1_HDR2_MATRIXO_PRE_OFFSET0_1 0x38b8
#define OSD1_HDR2_MATRIXO_PRE_OFFSET2 0x38b9
#define OSD1_HDR2_MATRIXI_CLIP 0x38ba
#define OSD1_HDR2_MATRIXO_CLIP 0x38bb
#define OSD1_HDR2_CGAIN_OFFT 0x38bc
#define OSD1_EOTF_LUT_ADDR_PORT 0x38be
#define OSD1_EOTF_LUT_DATA_PORT 0x38bf
#define OSD1_OETF_LUT_ADDR_PORT 0x38c0
#define OSD1_OETF_LUT_DATA_PORT 0x38c1
#define OSD1_CGAIN_LUT_ADDR_PORT 0x38c2
#define OSD1_CGAIN_LUT_DATA_PORT 0x38c3
#define OSD1_HDR2_CGAIN_COEF0 0x38c4
#define OSD1_HDR2_CGAIN_COEF1 0x38c5
#define OSD1_OGAIN_LUT_ADDR_PORT 0x38c6
#define OSD1_OGAIN_LUT_DATA_PORT 0x38c7
#define OSD1_HDR2_ADPS_CTRL 0x38c8
#define OSD1_HDR2_ADPS_ALPHA0 0x38c9
#define OSD1_HDR2_ADPS_ALPHA1 0x38ca
#define OSD1_HDR2_ADPS_BETA0 0x38cb
#define OSD1_HDR2_ADPS_BETA1 0x38cc
#define OSD1_HDR2_ADPS_BETA2 0x38cd
#define OSD1_HDR2_ADPS_COEF0 0x38ce
#define OSD1_HDR2_ADPS_COEF1 0x38cf
#define OSD1_HDR2_GMUT_CTRL 0x38d0
#define OSD1_HDR2_GMUT_COEF0 0x38d1
#define OSD1_HDR2_GMUT_COEF1 0x38d2
#define OSD1_HDR2_GMUT_COEF2 0x38d3
#define OSD1_HDR2_GMUT_COEF3 0x38d4
#define OSD1_HDR2_GMUT_COEF4 0x38d5
#define OSD1_HDR2_PIPE_CTRL1 0x38d6
#define OSD1_HDR2_PIPE_CTRL2 0x38d7
#define OSD1_HDR2_PIPE_CTRL3 0x38d8
#define OSD1_HDR2_PROC_WIN1 0x38d9
#define OSD1_HDR2_PROC_WIN2 0x38da
#define OSD1_HDR2_MATRIXI_EN_CTRL 0x38db
#define OSD1_HDR2_MATRIXO_EN_CTRL 0x38dc
#endif

1365
drivers/amlogic/media/enhancement/amvecm/set_hdr2_v0.c Normal file
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File diff suppressed because it is too large Load Diff

90
drivers/amlogic/media/enhancement/amvecm/set_hdr2_v0.h Normal file
View File

@@ -0,0 +1,90 @@
#include <linux/types.h>
#ifndef MAX
#define MAX(x1, x2) (double)(x1 > x2 ? x1 : x2)
#endif
#ifndef POW
#define POW(x1, x2) (int64_t)(pow((double)x1, (double)x2))
#endif
#ifndef LOG2
#define LOG2(x) (int)(x == 0 ? 0 : log2((long long)x))
#endif
#define FLTZERO 0xfc000/*float zero*/
#define peak_out 10000/* luma out*/
#define peak_in 1000/* luma in*/
/* 0:hdr10 peak_in input to hdr10 peak_out,*/
/*1:hdr peak_in->gamma,2:gamma->hdr peak out*/
#define fmt_io 2
#define precision 14/* freeze*/
/*input data bitwidth : 12 (VD1 OSD1 VD2)*/
/*10 (VDIN & DI)*/
#define IE_BW 12
#define OE_BW 12/*same IE_BW*/
#define O_BW 32/*freeze*/
#define maxbit 33/*freeze*/
#define OGAIN_BW 12/*freeze*/
int64_t FloatRev(int64_t iA);
int64_t FloatCon(int64_t iA, int MOD);
enum hdr_module_sel {
VD1_HDR = 0x1,
VD2_HDR = 0x2,
OSD1_HDR = 0x4,
VDIN0_HDR = 0x8,
VDIN1_HDR = 0x10,
DI_HDR = 0x20,
HDR_MAX
};
enum hdr_matrix_sel {
HDR_IN_MTX = 0x1,
HDR_GAMUT_MTX = 0x2,
HDR_OUT_MTX = 0x4,
HDR_MTX_MAX
};
enum hdr_lut_sel {
HDR_EOTF_LUT = 0x1,
HDR_OOTF_LUT = 0x2,
HDR_OETF_LUT = 0x4,
HDR_CGAIN_LUT = 0x8,
HDR_LUT_MAX
};
enum hdr_process_sel {
HDR_SDR = 0x1,
SDR_HDR = 0x2,
HDR_BYPASS = 0x4,
HDR_p_MAX
};
#define MTX_ON 1
#define MTX_OFF 0
#define MTX_ONLY 1
#define HDR_ONLY 0
#define LUT_ON 1
#define LUT_OFF 0
#define HDR2_EOTF_LUT_SIZE 143
#define HDR2_OOTF_LUT_SIZE 149
#define HDR2_OETF_LUT_SIZE 149
#define HDR2_CGAIN_LUT_SIZE 65
typedef int64_t(*MenuFun)(int64_t);
void eotf_float_gen(int64_t *o_out, MenuFun eotf);
void oetf_float_gen(int64_t *bin_e, MenuFun oetf);
void nolinear_lut_gen(int64_t *bin_c, MenuFun cgain);
extern void hdrbypass_func(enum hdr_module_sel module_sel);
extern void hdr2sdr_func(enum hdr_module_sel module_sel);
extern void sdr2hdr_func(enum hdr_module_sel module_sel);