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rk3368 dtsi: modify dtsi for display module

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Signed-off-by: hjc <hjc@rock-chips.com>
This commit is contained in:
hjc
2014-12-09 12:19:52 +08:00
committed by Huang, Tao
parent 7d40b12c2c
commit 96808e0a17
2 changed files with 130 additions and 0 deletions
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97
arch/arm64/boot/dts/rk3368-fpga.dts
View File

@@ -1,6 +1,7 @@
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/rkfb/rk_fb.h>
/ {
compatible = "rockchip,rk3368";
@@ -68,4 +69,100 @@
reg = <0x0 0xffb71000 0 0x1000>,
<0x0 0xffb72000 0 0x1000>;
};
ion {
compatible = "rockchip,ion";
#address-cells = <1>;
#size-cells = <0>;
ion_cma: rockchip,ion-heap@1 { /* CMA HEAP */
compatible = "rockchip,ion-heap";
rockchip,ion_heap = <1>;
reg = <0x00000000 0x08000000>; /* 512MB */
};
rockchip,ion-heap@3 { /* VMALLOC HEAP */
compatible = "rockchip,ion-heap";
rockchip,ion_heap = <3>;
};
};
fb: fb {
compatible = "rockchip,rk-fb";
rockchip,disp-mode = <NO_DUAL>;
};
rk_screen: rk_screen {
compatible = "rockchip,screen";
disp_timings: display-timings {
native-mode = <&timing0>;
timing0: timing0 {
screen-type = <SCREEN_RGB>;
out-face = <OUT_P888>;
color-mode = <COLOR_RGB>;
clock-frequency = <27000000>;
hactive = <800>;
vactive = <480>;
hback-porch = <206>;
hfront-porch = <1>;
vback-porch = <25>;
vfront-porch = <10>;
hsync-len = <10>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
};
};
};
lvds: lvds@ff968000 {
compatible = "rockchip,rk3368-lvds";
reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600b0 0x0 0x01>;
//reg = <0xff968000 0x4000>, <0xff9600b0 0x01>;
reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
//clocks = <&dummy>, <&dummy>;
//clock-names = "pclk_lvds", "pclk_lvds_ctl";
status = "okay";
};
lcdc: lcdc@ff930000 {
compatible = "rockchip,rk3368-lcdc";
rockchip,prop = <PRMRY>;
rockchip,pwr18 = <0>;
rockchip,iommu-enabled = <0>;
//reg = <0xff930000 0x10000>;
reg = <0x0 0xff930000 0x0 0x10000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
//pinctrl-names = "default", "gpio";
//pinctrl-0 = <&lcdc_lcdc>;
//pinctrl-1 = <&lcdc_gpio>;
status = "okay";
//clocks = <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>;
//clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc", "sclk_lcdc";
power_ctr: power_ctr {
rockchip,debug = <0>;
/*
lcd_en:lcd_en {
rockchip,power_type = <GPIO>;
gpios = <&gpio7 GPIO_A3 GPIO_ACTIVE_HIGH>;
rockchip,delay = <10>;
};
*/
/*lcd_cs:lcd_cs {
rockchip,power_type = <REGULATOR>;
rockchip,delay = <10>;
};
lcd_rst:lcd_rst {
rockchip,power_type = <GPIO>;
gpios = <&gpio3 GPIO_D6 GPIO_ACTIVE_HIGH>;
rockchip,delay = <5>;
};*/
};
};
};

33
arch/arm64/boot/dts/rk3368.dtsi
View File

@@ -6,6 +6,7 @@
#include <dt-bindings/pinctrl/rockchip-rk3288.h>
#include "rk3368-clocks.dtsi"
#include <dt-bindings/rkfb/rk_fb.h>
/ {
compatible = "rockchip,rk3368";
@@ -249,6 +250,14 @@
rockchip,check-idle = <1>;
status = "disabled";
};
fb: fb{
compatible = "rockchip,rk-fb";
rockchip,disp-mode = <NO_DUAL>;
};
rk_screen: rk_screen{
compatible = "rockchip,screen";
};
uart_bt: serial@ff180000 {
compatible = "rockchip,serial";
@@ -1000,4 +1009,28 @@
};
};
};
lvds: lvds@ff968000 {
compatible = "rockchip,rk3368-lvds";
reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600b0 0x0 0x01>;
reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
clocks = <&dummy>, <&dummy>;
clock-names = "pclk_lvds", "pclk_lvds_ctl";
status = "disabled";
};
lcdc: lcdc@ff930000 {
compatible = "rockchip,rk3368-lcdc";
rockchip,prop = <PRMRY>;
rockchip,pwr18 = <0>;
rockchip,iommu-enabled = <0>;
reg = <0x0 0xff930000 0x0 0x10000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&lcdc_lcdc>;
pinctrl-1 = <&lcdc_gpio>;
status = "disabled";
clocks = <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>;
clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc", "sclk_pll";
};
};