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https://github.com/hardkernel/linux.git
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media: rockchip: isp: rawwr and rawrd memory mode
Three mode: 0: raw12/raw10/raw8 8bit memory compact 1: raw12/raw10 16bit memory one pixel big endian for rv1126/rv1109 |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| | 3| 2| 1| 0| -| -| -| -|11|10| 9| 8| 7| 6| 5| 4| little align for rk356x |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| | -| -| -| -|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| 2: raw12/raw10 16bit memory one pixel big align for rv1126/rv1109/rk356x |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| |11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| -| -| -| -| Change-Id: Iabd5600d1a880057f0a20e187b15d337079a14c6 Signed-off-by: Cai YiWei <cyw@rock-chips.com> Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
This commit is contained in:
@@ -217,6 +217,7 @@ int hdr_config_dmatx(struct rkisp_device *dev)
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{
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struct rkisp_stream *stream;
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struct v4l2_pix_format_mplane pixm;
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u32 memory = 0;
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if (atomic_inc_return(&dev->hdr.refcnt) > 1 ||
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!dev->active_sensor ||
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@@ -266,6 +267,7 @@ int hdr_config_dmatx(struct rkisp_device *dev)
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stream->ops->config_mi(stream);
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if (!dev->dmarx_dev.trigger) {
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memory = stream->memory;
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pixm = stream->out_fmt;
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stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD2];
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rkisp_dmarx_set_fmt(stream, pixm);
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@@ -274,7 +276,7 @@ int hdr_config_dmatx(struct rkisp_device *dev)
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}
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if (dev->hdr.op_mode != HDR_NORMAL && !dev->dmarx_dev.trigger) {
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raw_rd_ctrl(dev->base_addr, dev->csi_dev.memory << 2);
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raw_rd_ctrl(dev->base_addr, memory << 2);
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if (pixm.width && pixm.height)
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rkisp_rawrd_set_pic_size(dev, pixm.width, pixm.height);
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}
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@@ -957,7 +959,7 @@ static int rkisp_set_fmt(struct rkisp_stream *stream,
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if ((dev->isp_ver == ISP_V20 ||
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dev->isp_ver == ISP_V21) &&
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!dev->csi_dev.memory &&
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!stream->memory &&
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fmt->fmt_type == FMT_BAYER &&
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stream->id != RKISP_STREAM_MP &&
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stream->id != RKISP_STREAM_SP)
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@@ -1128,6 +1130,50 @@ static int rkisp_enum_framesizes(struct file *file, void *prov,
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return 0;
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}
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static long rkisp_ioctl_default(struct file *file, void *fh,
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bool valid_prio, unsigned int cmd, void *arg)
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{
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struct rkisp_stream *stream = video_drvdata(file);
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long ret = 0;
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if (!arg)
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return -EINVAL;
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switch (cmd) {
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case RKISP_CMD_GET_CSI_MEMORY_MODE:
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if (stream->id != RKISP_STREAM_DMATX0 &&
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stream->id != RKISP_STREAM_DMATX1 &&
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stream->id != RKISP_STREAM_DMATX2 &&
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stream->id != RKISP_STREAM_DMATX3)
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ret = -EINVAL;
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else if (stream->memory == 0)
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*(int *)arg = CSI_MEM_COMPACT;
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else if (stream->memory == SW_CSI_RAW_WR_SIMG_MODE)
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*(int *)arg = CSI_MEM_WORD_BIG_ALIGN;
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else
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*(int *)arg = CSI_MEM_WORD_LITTLE_ALIGN;
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break;
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case RKISP_CMD_SET_CSI_MEMORY_MODE:
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if (stream->id != RKISP_STREAM_DMATX0 &&
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stream->id != RKISP_STREAM_DMATX1 &&
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stream->id != RKISP_STREAM_DMATX2 &&
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stream->id != RKISP_STREAM_DMATX3)
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ret = -EINVAL;
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else if (*(int *)arg == CSI_MEM_COMPACT)
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stream->memory = 0;
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else if (*(int *)arg == CSI_MEM_WORD_BIG_ALIGN)
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stream->memory = SW_CSI_RAW_WR_SIMG_MODE;
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else
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stream->memory =
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SW_CSI_RWA_WR_SIMG_SWP | SW_CSI_RAW_WR_SIMG_MODE;
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break;
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default:
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ret = -EINVAL;
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}
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return ret;
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}
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static int rkisp_enum_frameintervals(struct file *file, void *fh,
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struct v4l2_frmivalenum *fival)
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{
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@@ -1362,6 +1408,7 @@ static const struct v4l2_ioctl_ops rkisp_v4l2_ioctl_ops = {
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.vidioc_querycap = rkisp_querycap,
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.vidioc_enum_frameintervals = rkisp_enum_frameintervals,
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.vidioc_enum_framesizes = rkisp_enum_framesizes,
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.vidioc_default = rkisp_ioctl_default,
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};
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void rkisp_unregister_stream_vdev(struct rkisp_stream *stream)
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@@ -225,6 +225,7 @@ struct rkisp_stream {
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unsigned int burst;
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atomic_t sequence;
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struct frame_debug_info dbg;
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u32 memory;
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union {
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struct rkisp_stream_sp sp;
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struct rkisp_stream_mp mp;
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@@ -539,7 +539,7 @@ static int dmatx3_config_mi(struct rkisp_stream *stream)
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vc = csi->sink[CSI_SRC_CH4 - 1].index;
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raw_wr_ctrl(stream,
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SW_CSI_RAW_WR_CH_EN(vc) |
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csi->memory |
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stream->memory |
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SW_CSI_RAW_WR_EN_ORG);
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mi_set_y_size(stream, in_size);
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mi_frame_end(stream);
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@@ -583,7 +583,7 @@ static int dmatx2_config_mi(struct rkisp_stream *stream)
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raw_wr_set_pic_offs(stream, 0);
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vc = csi->sink[CSI_SRC_CH3 - 1].index;
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val = SW_CSI_RAW_WR_CH_EN(vc);
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val |= csi->memory;
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val |= stream->memory;
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if (dev->hdr.op_mode != HDR_NORMAL)
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val |= SW_CSI_RAW_WR_EN_ORG;
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raw_wr_ctrl(stream, val);
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@@ -627,7 +627,7 @@ static int dmatx1_config_mi(struct rkisp_stream *stream)
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raw_wr_set_pic_offs(stream, 0);
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vc = csi->sink[CSI_SRC_CH2 - 1].index;
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val = SW_CSI_RAW_WR_CH_EN(vc);
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val |= csi->memory;
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val |= stream->memory;
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if (dev->hdr.op_mode != HDR_NORMAL)
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val |= SW_CSI_RAW_WR_EN_ORG;
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raw_wr_ctrl(stream, val);
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@@ -675,7 +675,7 @@ static int dmatx0_config_mi(struct rkisp_stream *stream)
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raw_wr_set_pic_offs(dmatx, 0);
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vc = csi->sink[CSI_SRC_CH1 - 1].index;
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val = SW_CSI_RAW_WR_CH_EN(vc);
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val |= csi->memory;
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val |= stream->memory;
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if (dev->hdr.op_mode != HDR_NORMAL)
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val |= SW_CSI_RAW_WR_EN_ORG;
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raw_wr_ctrl(dmatx, val);
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@@ -503,7 +503,7 @@ static int dmatx3_config_mi(struct rkisp_stream *stream)
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vc = csi->sink[CSI_SRC_CH4 - 1].index;
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raw_wr_ctrl(stream,
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SW_CSI_RAW_WR_CH_EN(vc) |
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csi->memory |
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stream->memory |
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SW_CSI_RAW_WR_EN_ORG);
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stream->u.dmatx.is_config = true;
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v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
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@@ -548,7 +548,7 @@ static int dmatx2_config_mi(struct rkisp_stream *stream)
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mi_raw_length(stream);
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vc = csi->sink[CSI_SRC_CH3 - 1].index;
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val = SW_CSI_RAW_WR_CH_EN(vc);
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val |= csi->memory;
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val |= stream->memory;
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if (dev->hdr.op_mode != HDR_NORMAL)
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val |= SW_CSI_RAW_WR_EN_ORG;
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raw_wr_ctrl(stream, val);
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@@ -591,7 +591,7 @@ static int dmatx0_config_mi(struct rkisp_stream *stream)
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mi_raw_length(stream);
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vc = csi->sink[CSI_SRC_CH1 - 1].index;
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val = SW_CSI_RAW_WR_CH_EN(vc);
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val |= csi->memory;
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val |= stream->memory;
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if (dev->hdr.op_mode != HDR_NORMAL)
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val |= SW_CSI_RAW_WR_EN_ORG;
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raw_wr_ctrl(stream, val);
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@@ -61,7 +61,6 @@ struct sink_info {
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* sink: csi link enable flags
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* mipi_di: Data Identifier (vc[7:6],dt[5:0])
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* tx_first: flags for dmatx first Y_STATE irq
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* memory: compact or big/little endian byte order for tx/rx
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*/
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struct rkisp_csi_device {
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struct rkisp_device *ispdev;
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@@ -73,7 +72,6 @@ struct rkisp_csi_device {
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u32 irq_cnt;
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u8 mipi_di[CSI_PAD_MAX - 1];
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u8 tx_first[HDR_DMA_MAX];
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u8 memory;
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};
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int rkisp_register_csi_subdev(struct rkisp_device *dev,
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@@ -347,7 +347,7 @@ static int rawrd_config_mi(struct rkisp_stream *stream)
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val |= CIF_CSI2_DT_RAW12;
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}
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rkisp_write(dev, CSI2RX_RAW_RD_CTRL,
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dev->csi_dev.memory << 2, false);
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stream->memory << 2, false);
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rkisp_write(dev, CSI2RX_DATA_IDS_1, val, false);
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rkisp_rawrd_set_pic_size(dev, stream->out_fmt.width,
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stream->out_fmt.height);
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@@ -719,7 +719,7 @@ static int rkisp_set_fmt(struct rkisp_stream *stream,
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if ((stream->ispdev->isp_ver == ISP_V20 ||
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stream->ispdev->isp_ver == ISP_V21) &&
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fmt->fmt_type == FMT_BAYER &&
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!stream->ispdev->csi_dev.memory &&
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!stream->memory &&
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stream->id != RKISP_STREAM_DMARX)
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bytesperline = ALIGN(width * fmt->bpp[i] / 8, 256);
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else
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@@ -834,6 +834,45 @@ static int rkisp_querycap(struct file *file, void *priv,
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return 0;
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}
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static long rkisp_ioctl_default(struct file *file, void *fh,
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bool valid_prio, unsigned int cmd, void *arg)
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{
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struct rkisp_stream *stream = video_drvdata(file);
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long ret = 0;
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switch (cmd) {
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case RKISP_CMD_GET_CSI_MEMORY_MODE:
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if (stream->id != RKISP_STREAM_RAWRD0 &&
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stream->id != RKISP_STREAM_RAWRD1 &&
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stream->id != RKISP_STREAM_RAWRD2)
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ret = -EINVAL;
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else if (stream->memory == 0)
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*(int *)arg = CSI_MEM_COMPACT;
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else if (stream->memory == SW_CSI_RAW_WR_SIMG_MODE)
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*(int *)arg = CSI_MEM_WORD_BIG_ALIGN;
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else
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*(int *)arg = CSI_MEM_WORD_LITTLE_ALIGN;
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break;
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case RKISP_CMD_SET_CSI_MEMORY_MODE:
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if (stream->id != RKISP_STREAM_RAWRD0 &&
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stream->id != RKISP_STREAM_RAWRD1 &&
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stream->id != RKISP_STREAM_RAWRD2)
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ret = -EINVAL;
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else if (*(int *)arg == CSI_MEM_COMPACT)
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stream->memory = 0;
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else if (*(int *)arg == CSI_MEM_WORD_BIG_ALIGN)
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stream->memory = SW_CSI_RAW_WR_SIMG_MODE;
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else
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stream->memory =
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SW_CSI_RWA_WR_SIMG_SWP | SW_CSI_RAW_WR_SIMG_MODE;
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break;
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default:
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ret = -EINVAL;
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}
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return ret;
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}
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static const struct v4l2_ioctl_ops rkisp_dmarx_ioctl = {
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.vidioc_reqbufs = vb2_ioctl_reqbufs,
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.vidioc_querybuf = vb2_ioctl_querybuf,
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@@ -849,6 +888,7 @@ static const struct v4l2_ioctl_ops rkisp_dmarx_ioctl = {
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.vidioc_s_fmt_vid_out_mplane = rkisp_s_fmt_vid_out_mplane,
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.vidioc_g_fmt_vid_out_mplane = rkisp_g_fmt_vid_out_mplane,
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.vidioc_querycap = rkisp_querycap,
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.vidioc_default = rkisp_ioctl_default,
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};
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static void rkisp_unregister_dmarx_video(struct rkisp_stream *stream)
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@@ -2465,15 +2465,6 @@ static long rkisp_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
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case RKISP_CMD_TRIGGER_READ_BACK:
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rkisp_rdbk_trigger_event(isp_dev, T_CMD_QUEUE, arg);
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break;
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case RKISP_CMD_CSI_MEMORY_MODE:
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if (*((int *)arg) == CSI_MEM_BYTE_BE)
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isp_dev->csi_dev.memory = SW_CSI_RWA_WR_SIMG_SWP |
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SW_CSI_RAW_WR_SIMG_MODE;
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else if (*((int *)arg) == CSI_MEM_BYTE_LE)
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isp_dev->csi_dev.memory = SW_CSI_RAW_WR_SIMG_MODE;
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else
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isp_dev->csi_dev.memory = 0;
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break;
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case RKISP_CMD_GET_SHARED_BUF:
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if (!IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP)) {
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ret = -ENOIOCTLCMD;
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@@ -2563,7 +2554,6 @@ static long rkisp_compat_ioctl32(struct v4l2_subdev *sd,
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struct rkisp_thunderboot_shmem shmem;
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struct isp2x_buf_idxfd idxfd;
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long ret = 0;
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int mode;
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if (!up && cmd != RKISP_CMD_FREE_SHARED_BUF)
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return -EINVAL;
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@@ -2574,11 +2564,6 @@ static long rkisp_compat_ioctl32(struct v4l2_subdev *sd,
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return -EFAULT;
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ret = rkisp_ioctl(sd, cmd, &trigger);
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break;
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case RKISP_CMD_CSI_MEMORY_MODE:
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if (copy_from_user(&mode, up, sizeof(int)))
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return -EFAULT;
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ret = rkisp_ioctl(sd, cmd, &mode);
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break;
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case RKISP_CMD_GET_SHARED_BUF:
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if (!IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP)) {
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ret = -ENOIOCTLCMD;
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@@ -12,12 +12,11 @@
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#define RKISP_API_VERSION KERNEL_VERSION(1, 6, 2)
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/****************ISP SUBDEV IOCTL*****************************/
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#define RKISP_CMD_TRIGGER_READ_BACK \
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_IOW('V', BASE_VIDIOC_PRIVATE + 0, struct isp2x_csi_trigger)
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#define RKISP_CMD_CSI_MEMORY_MODE \
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_IOW('V', BASE_VIDIOC_PRIVATE + 1, int)
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#define RKISP_CMD_GET_SHARED_BUF \
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_IOR('V', BASE_VIDIOC_PRIVATE + 2, struct rkisp_thunderboot_resmem)
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@@ -36,6 +35,16 @@
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#define RKISP_CMD_GET_FBCBUF_FD \
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_IOR('V', BASE_VIDIOC_PRIVATE + 7, struct isp2x_buf_idxfd)
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/****************ISP VIDEO IOCTL******************************/
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#define RKISP_CMD_GET_CSI_MEMORY_MODE \
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_IOR('V', BASE_VIDIOC_PRIVATE + 100, int)
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#define RKISP_CMD_SET_CSI_MEMORY_MODE \
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_IOW('V', BASE_VIDIOC_PRIVATE + 101, int)
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/*************************************************************/
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#define ISP2X_ID_DPCC (0)
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#define ISP2X_ID_BLS (1)
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#define ISP2X_ID_SDG (2)
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@@ -231,11 +240,25 @@ struct isp2x_csi_trigger {
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enum isp2x_trigger_mode mode;
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} __attribute__ ((packed));
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enum isp2x_csi_memory {
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/* isp csi dmatx/dmarx memory mode
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* 0: raw12/raw10/raw8 8bit memory compact
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* 1: raw12/raw10 16bit memory one pixel
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* big endian for rv1126/rv1109
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* |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0|
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* | 3| 2| 1| 0| -| -| -| -|11|10| 9| 8| 7| 6| 5| 4|
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* little align for rk356x
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* |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0|
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* | -| -| -| -|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0|
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* 2: raw12/raw10 16bit memory one pixel
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* big align for rv1126/rv1109/rk356x
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* |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0|
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* |11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| -| -| -| -|
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*/
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enum isp_csi_memory {
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CSI_MEM_COMPACT = 0,
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CSI_MEM_BYTE_BE,
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CSI_MEM_BYTE_LE,
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CSI_MEM_MAX,
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CSI_MEM_WORD_BIG_END = 1,
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CSI_MEM_WORD_LITTLE_ALIGN = 1,
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CSI_MEM_WORD_BIG_ALIGN = 2,
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};
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struct isp2x_ispgain_buf {
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