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Merge commit 'c10152d3e7dd7eea6c9e65cdc8fc97d46692fec1'

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* commit 'c10152d3e7dd7eea6c9e65cdc8fc97d46692fec1':
  media: i2c: sc450ai: add 1344X760 config
  drm/rockchip: vop2: force to disable cluster-win1 when cluster-win0 is disabled
  ARM: dts: rockchip: rv1106: add dvbm node to isp
  media: rockchip: isp: frame start to check and config next buf
  arm64: dts: rockchip: rk3588-vehicle-evb: set 40ms delay for display
  mfd: display-serdes: rohm gpio0 support 1MHZ used for pwm
  mfd: display-serdes: change default pinctrl to init

Change-Id: I9d5e4ab36103192d4657c8d4c4bf4e316396700f
This commit is contained in:
Tao Huang
2024-01-19 21:14:17 +08:00
parent f302276d4e c10152d3e7
commit 972ef7bb84
14 changed files with 296 additions and 75 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/boot/dts/rv1106.dtsi
View File

@@ -314,18 +314,21 @@
rkisp_vir1: rkisp-vir1 {
compatible = "rockchip,rkisp-vir";
rockchip,hw = <&rkisp>;
dvbm = <&rkdvbm>;
status = "disabled";
};
rkisp_vir2: rkisp-vir2 {
compatible = "rockchip,rkisp-vir";
rockchip,hw = <&rkisp>;
dvbm = <&rkdvbm>;
status = "disabled";
};
rkisp_vir3: rkisp-vir3 {
compatible = "rockchip,rkisp-vir";
rockchip,hw = <&rkisp>;
dvbm = <&rkdvbm>;
status = "disabled";
};

22
arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display-v20.dtsi
View File

@@ -652,6 +652,7 @@
02a8 0003
02a9 0004
02aa 0005
02af 0002 //gpio0 1MHZ
0045 0080
0046 0007
0047 0080
@@ -880,9 +881,9 @@
function = "DES_TO_SER_GPIO3";
};
100ms-delay {
40ms-delay {
pins = "BU18RL82_GPIO1";
function = "DELAY_100MS";
function = "DELAY_40MS";
};
lcd-pwr-en {
@@ -972,6 +973,7 @@
002d 0018
0030 0018
0033 0018
02af 0002 //gpio0 1MHZ
0045 0080
0046 0007
004b 0038
@@ -1178,9 +1180,9 @@
function = "DES_TO_SER_GPIO3";
};
100ms-delay {
40ms-delay {
pins = "BU18RL82_GPIO1";
function = "DELAY_100MS";
function = "DELAY_40MS";
};
lcd-pwr-en {
@@ -1290,6 +1292,7 @@
0275 0020
0296 0004
0297 000d
02af 0002 //gpio0 1MHZ
02b2 00c8
02b4 0001
02b8 00ff
@@ -1487,9 +1490,9 @@
function = "DES_TO_SER_GPIO3";
};
100ms-delay {
40ms-delay {
pins = "BU18RL82_GPIO1";
function = "DELAY_100MS";
function = "DELAY_40MS";
};
lcd-pwr-en {
@@ -1595,6 +1598,7 @@
02a8 0003
02a9 0004
02aa 0005
02af 0002 //gpio0 1MHZ
0045 0080
0046 0007
0047 0080
@@ -1826,9 +1830,9 @@
function = "DES_TO_SER_GPIO3";
};
100ms-delay {
40ms-delay {
pins = "BU18RL82_GPIO1";
function = "DELAY_100MS";
function = "DELAY_40MS";
};
lcd-pwr-en {
@@ -1930,6 +1934,7 @@
0275 0020
0296 0004
0297 000d
02af 0002 //gpio0 1MHZ
02b2 00c8
02b4 0001
02b8 00ff
@@ -2198,6 +2203,7 @@
002d 0018
0030 0018
0033 0018
02af 0002 //gpio0 1MHZ
0045 0080
0046 0007
004b 0038

24
arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-mfd-display-maxim-split.dtsi
View File

@@ -693,9 +693,9 @@
pins = "MAX96752_GPIO2";
function = "DES_TXID8_TO_SER";
};
100ms-delay {
40ms-delay {
pins = "MAX96752_GPIO15";
function = "DELAY_100MS";
function = "DELAY_40MS";
};
lcd-pwr-on {
pins = "MAX96752_GPIO3";
@@ -823,9 +823,9 @@
pins = "MAX96752_GPIO2";
function = "DES_TXID14_TO_SER";
};
100ms-delay {
40ms-delay {
pins = "MAX96752_GPIO15";
function = "DELAY_100MS";
function = "DELAY_40MS";
};
lcd-pwr-on {
pins = "MAX96752_GPIO3";
@@ -1367,9 +1367,9 @@
pins = "MAX96752_GPIO2";
function = "DES_TXID1_TO_SER";
};
100ms-delay {
40ms-delay {
pins = "MAX96752_GPIO15";
function = "DELAY_100MS";
function = "DELAY_40MS";
};
lcd-pwr-on {
pins = "MAX96752_GPIO3";
@@ -1495,9 +1495,9 @@
pins = "MAX96752_GPIO2";
function = "DES_TXID4_TO_SER";
};
100ms-delay {
40ms-delay {
pins = "MAX96752_GPIO15";
function = "DELAY_100MS";
function = "DELAY_40MS";
};
lcd-pwr-on {
pins = "MAX96752_GPIO3";
@@ -2044,9 +2044,9 @@
pins = "MAX96752_GPIO2";
function = "DES_TXID1_TO_SER";
};
100ms-delay {
40ms-delay {
pins = "MAX96752_GPIO15";
function = "DELAY_100MS";
function = "DELAY_40MS";
};
lcd-pwr-on {
pins = "MAX96752_GPIO3";
@@ -2173,9 +2173,9 @@
pins = "MAX96752_GPIO2";
function = "DES_TXID4_TO_SER";
};
100ms-delay {
40ms-delay {
pins = "MAX96752_GPIO15";
function = "DELAY_100MS";
function = "DELAY_40MS";
};
lcd-pwr-on {
pins = "MAX96752_GPIO3";

22
arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-mfd-display-rohm.dtsi
View File

@@ -683,6 +683,7 @@
02a8 0003
02a9 0004
02aa 0005
02af 0002 //gpio0 1MHZ
0045 0080
0046 0007 //1920
004b 00d0
@@ -880,9 +881,9 @@
function = "DES_TO_SER_GPIO3";
};
100ms-delay {
40ms-delay {
pins = "BU18RL82_GPIO1";
function = "DELAY_100MS";
function = "DELAY_40MS";
};
lcd-pwr-en {
@@ -1022,6 +1023,7 @@
02a8 0003
02a9 0004
02aa 0005
02af 0002 //gpio0 1MHZ
0045 0080
0046 0007 //1920
004b 00d0
@@ -1219,9 +1221,9 @@
function = "DES_TO_SER_GPIO3";
};
100ms-delay {
40ms-delay {
pins = "BU18RL82_GPIO1";
function = "DELAY_100MS";
function = "DELAY_40MS";
};
lcd-pwr-en {
@@ -1349,6 +1351,7 @@
0275 0020
0296 0004
0297 000d
02af 0002 //gpio0 1MHZ
02b2 00c8
02b4 0001
02b8 00ff
@@ -1552,9 +1555,9 @@
function = "DES_TO_SER_GPIO3";
};
100ms-delay {
40ms-delay {
pins = "BU18RL82_GPIO1";
function = "DELAY_100MS";
function = "DELAY_40MS";
};
lcd-pwr-en {
@@ -1700,6 +1703,7 @@
02a8 0003
02a9 0004
02aa 0005
02af 0002 //gpio0 1MHZ
0045 0080
0046 0007 //1920
004b 00d0
@@ -1899,9 +1903,9 @@
function = "DES_TO_SER_GPIO3";
};
100ms-delay {
40ms-delay {
pins = "BU18RL82_GPIO1";
function = "DELAY_100MS";
function = "DELAY_40MS";
};
lcd-pwr-en {
@@ -2024,6 +2028,7 @@
0275 0020
0296 0004
0297 000d
02af 0002 //gpio0 1MHZ
02b2 00c8
02b4 0001
02b8 00ff
@@ -2335,6 +2340,7 @@
02a8 0003
02a9 0004
02aa 0005
02af 0002 //gpio0 1MHZ
0045 0080
0046 0007 //1920
004b 00d0

7
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -4544,6 +4544,13 @@ static int vop2_cluster_two_win_mode_check(struct drm_plane_state *pstate)
main_pstate = drm_atomic_get_new_plane_state(state, &main_win->base);
if (!main_pstate || !main_pstate->fb) {
DRM_INFO("force to disable %s when cluster-win0 is disabled\n", win->name);
pstate->visible = false;
return 0;
}
if (pstate->fb->modifier != main_pstate->fb->modifier) {
DRM_ERROR("%s(fb->modifier: 0x%llx) must use same data layout as %s(fb->modifier: 0x%llx)\n",
win->name, pstate->fb->modifier, main_win->name, main_pstate->fb->modifier);

215
drivers/media/i2c/sc450ai.c
View File

@@ -174,6 +174,199 @@ static const struct regval sc450ai_global_regs[] = {
{REG_NULL, 0x00},
};
/*
* Xclk 27Mhz
* max_framerate 120fps
* mipi_datarate per lane 720Mbps, 2lane
* binning to 1344x760
*/
static const struct regval sc450ai_linear_10_1344x760_120fps_regs[] = {
{0x0103, 0x01},
{0x0100, 0x00},
{0x36e9, 0x80},
{0x36f9, 0x80},
{0x3018, 0x3a},
{0x3019, 0x0c},
{0x301c, 0x78},
{0x301f, 0x75},
{0x302e, 0x00},
{0x3208, 0x05},
{0x3209, 0x40},
{0x320a, 0x02},
{0x320b, 0xf8},
{0x320c, 0x03},
{0x320d, 0xa8},
{0x320e, 0x03},
{0x320f, 0x0c},
{0x3211, 0x04},
{0x3213, 0x04},
{0x3214, 0x11},
{0x3215, 0x31},
{0x3220, 0x01},
{0x3223, 0xc0},
{0x3253, 0x10},
{0x325f, 0x44},
{0x3274, 0x09},
{0x3280, 0x01},
{0x3301, 0x08},
{0x3306, 0x24},
{0x3309, 0x60},
{0x330b, 0x64},
{0x330d, 0x30},
{0x3315, 0x00},
{0x331f, 0x59},
{0x335d, 0x60},
{0x3364, 0x56},
{0x338f, 0x80},
{0x3390, 0x08},
{0x3391, 0x18},
{0x3392, 0x38},
{0x3393, 0x0a},
{0x3394, 0x10},
{0x3395, 0x18},
{0x3396, 0x08},
{0x3397, 0x18},
{0x3398, 0x38},
{0x3399, 0x0f},
{0x339a, 0x12},
{0x339b, 0x14},
{0x339c, 0x18},
{0x33af, 0x18},
{0x360f, 0x13},
{0x3621, 0xec},
{0x3627, 0xa0},
{0x3630, 0x90},
{0x3633, 0x56},
{0x3637, 0x1d},
{0x3638, 0x0a},
{0x363c, 0x0f},
{0x363d, 0x0f},
{0x363e, 0x08},
{0x3670, 0x4a},
{0x3671, 0xe0},
{0x3672, 0xe0},
{0x3673, 0xe0},
{0x3674, 0xb0},
{0x3675, 0x88},
{0x3676, 0x8c},
{0x367a, 0x48},
{0x367b, 0x58},
{0x367c, 0x48},
{0x367d, 0x58},
{0x3690, 0x34},
{0x3691, 0x43},
{0x3692, 0x44},
{0x3699, 0x03},
{0x369a, 0x0f},
{0x369b, 0x1f},
{0x369c, 0x40},
{0x369d, 0x48},
{0x36a2, 0x48},
{0x36a3, 0x78},
{0x36b0, 0x54},
{0x36b1, 0x75},
{0x36b2, 0x35},
{0x36b3, 0x48},
{0x36b4, 0x78},
{0x36b7, 0xa0},
{0x36b8, 0xa0},
{0x36b9, 0x20},
{0x36bd, 0x40},
{0x36be, 0x48},
{0x36d0, 0x20},
{0x36e0, 0x08},
{0x36e1, 0x08},
{0x36e2, 0x12},
{0x36e3, 0x48},
{0x36e4, 0x78},
{0x36fa, 0x0d},
{0x36fb, 0xa4},
{0x36fc, 0x00},
{0x36fd, 0x24},
{0x3907, 0x00},
{0x3908, 0x41},
{0x391e, 0x01},
{0x391f, 0x11},
{0x3933, 0x82},
{0x3934, 0x0b},
{0x3935, 0x02},
{0x3936, 0x5e},
{0x3937, 0x76},
{0x3938, 0x78},
{0x3939, 0x00},
{0x393a, 0x28},
{0x393b, 0x00},
{0x393c, 0x1d},
{0x3e00, 0x00},
{0x3e01, 0x61},
{0x3e02, 0x00},
{0x3e03, 0x0b},
{0x3e08, 0x03},
{0x3e1b, 0x2a},
{0x440e, 0x02},
{0x4509, 0x20},
{0x4837, 0x16},
{0x5000, 0x4e},
{0x5001, 0x44},
{0x5780, 0x76},
{0x5784, 0x08},
{0x5785, 0x04},
{0x5787, 0x0a},
{0x5788, 0x0a},
{0x5789, 0x0a},
{0x578a, 0x0a},
{0x578b, 0x0a},
{0x578c, 0x0a},
{0x578d, 0x40},
{0x5790, 0x08},
{0x5791, 0x04},
{0x5792, 0x04},
{0x5793, 0x08},
{0x5794, 0x04},
{0x5795, 0x04},
{0x5799, 0x46},
{0x579a, 0x77},
{0x57a1, 0x04},
{0x57a8, 0xd0},
{0x57aa, 0x2a},
{0x57ab, 0x7f},
{0x57ac, 0x00},
{0x57ad, 0x00},
{0x5900, 0x01},
{0x5901, 0x04},
{0x59e0, 0xfe},
{0x59e1, 0x40},
{0x59e2, 0x3f},
{0x59e3, 0x38},
{0x59e4, 0x30},
{0x59e5, 0x3f},
{0x59e6, 0x38},
{0x59e7, 0x30},
{0x59e8, 0x3f},
{0x59e9, 0x3c},
{0x59ea, 0x38},
{0x59eb, 0x3f},
{0x59ec, 0x3c},
{0x59ed, 0x38},
{0x59ee, 0xfe},
{0x59ef, 0x40},
{0x59f4, 0x3f},
{0x59f5, 0x38},
{0x59f6, 0x30},
{0x59f7, 0x3f},
{0x59f8, 0x38},
{0x59f9, 0x30},
{0x59fa, 0x3f},
{0x59fb, 0x3c},
{0x59fc, 0x38},
{0x59fd, 0x3f},
{0x59fe, 0x3c},
{0x59ff, 0x38},
{0x36e9, 0x44},
{0x36f9, 0x20},
{REG_NULL, 0x00},
};
/*
* Xclk 27Mhz
* max_framerate 60fps
@@ -374,6 +567,23 @@ static const struct sc450ai_mode supported_modes[] = {
.link_freq_idx = 0,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
},
{
.width = 1344,
.height = 760,
.max_fps = {
.numerator = 10000,
.denominator = 1200000,
},
.exp_def = 0x0080,
.hts_def = 0x03a8,
.vts_def = 0x030c,
.bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
.reg_list = sc450ai_linear_10_1344x760_120fps_regs,
.hdr_mode = NO_HDR,
.xvclk_freq = 27000000,
.link_freq_idx = 0,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
},
};
static const s64 link_freq_menu_items[] = {
@@ -1557,7 +1767,10 @@ static int sc450ai_probe(struct i2c_client *client,
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
pm_runtime_idle(dev);
if (sc450ai->is_thunderboot)
pm_runtime_get_sync(dev);
else
pm_runtime_idle(dev);
return 0;

39
drivers/media/platform/rockchip/isp/capture_v32.c
View File

@@ -1081,20 +1081,20 @@ static void update_mi(struct rkisp_stream *stream)
if (!ISP3X_ISP_OUT_LINE(rkisp_read(dev, ISP3X_ISP_DEBUG2, true))) {
stream->ops->enable_mi(stream);
stream_self_update(stream);
if (!stream->curr_buf) {
stream->curr_buf = stream->next_buf;
stream->next_buf = NULL;
}
/* maybe no next buf to preclose mi */
stream->ops->disable_mi(stream);
} else if (stream->is_pause) {
} else {
/* isp working and mi closed
* config buf and enable mi, capture at next frame
*/
stream->ops->enable_mi(stream);
stream->is_pause = false;
}
} else if (stream->is_pause) {
if (!stream->curr_buf) {
stream->curr_buf = stream->next_buf;
stream->next_buf = NULL;
}
} else {
/* isp working and mi no to close
* config buf will auto update at frame end
*/
@@ -1143,11 +1143,12 @@ static void update_mi(struct rkisp_stream *stream)
}
v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
"%s stream:%d Y:0x%x CB:0x%x | Y_SHD:0x%x\n",
__func__, stream->id,
"%s stream:%d cur:%p next:%p Y:0x%x CB:0x%x | Y_SHD:0x%x pause:%d stop:%d\n",
__func__, stream->id, stream->curr_buf, stream->next_buf,
rkisp_read(dev, stream->config->mi.y_base_ad_init, false),
rkisp_read(dev, stream->config->mi.cb_base_ad_init, false),
rkisp_read(dev, stream->config->mi.y_base_ad_shd, true));
rkisp_read(dev, stream->config->mi.y_base_ad_shd, true),
stream->is_pause, stream->ops->is_stream_stopped(stream));
}
static int set_mirror_flip(struct rkisp_stream *stream)
@@ -1376,17 +1377,16 @@ static int mi_frame_start(struct rkisp_stream *stream, u32 mis)
rkisp_stream_config_rsz(stream, false);
stream->is_crop_upd = false;
}
/* update buf for multi sensor at readback */
if (!mis && !stream->ispdev->hw_dev->is_single &&
!stream->curr_buf &&
!list_empty(&stream->buf_queue)) {
if (!list_empty(&stream->buf_queue) &&
((dev->hw_dev->is_single && !stream->next_buf) ||
(!dev->hw_dev->is_single && !stream->curr_buf))) {
stream->next_buf = list_first_entry(&stream->buf_queue,
struct rkisp_buffer, queue);
list_del(&stream->next_buf->queue);
stream->ops->update_mi(stream);
}
/* check frame loss */
if (mis && stream->ops->is_stream_stopped(stream))
if (stream->ops->is_stream_stopped(stream))
stream->dbg.frameloss++;
}
spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
@@ -1678,16 +1678,7 @@ static void rkisp_buf_queue(struct vb2_buffer *vb)
stream->id, ispbuf->buff_addr[0]);
spin_lock_irqsave(&stream->vbq_lock, lock_flags);
/* single sensor with pingpong buf, update next if need */
if (dev->hw_dev->is_single &&
stream->id != RKISP_STREAM_VIR &&
stream->id != RKISP_STREAM_LUMA &&
stream->streaming && !stream->next_buf) {
stream->next_buf = ispbuf;
stream->ops->update_mi(stream);
} else {
list_add_tail(&ispbuf->queue, &stream->buf_queue);
}
list_add_tail(&ispbuf->queue, &stream->buf_queue);
spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
}

2
drivers/media/platform/rockchip/isp/dev.c
View File

@@ -1165,7 +1165,7 @@ static void rkisp_pm_complete(struct device *dev)
}
for (i = 0; i < RKISP_MAX_STREAM; i++) {
stream = &isp_dev->cap_dev.stream[i];
if (i == RKISP_STREAM_VIR || !stream->streaming || !stream->curr_buf)
if (i == RKISP_STREAM_VIR || !stream->streaming)
continue;
/* skip first frame due to hw no reference frame information */
if (isp_dev->is_first_double)

11
drivers/media/platform/rockchip/isp/isp_rockit.c
View File

@@ -191,16 +191,7 @@ int rkisp_rockit_buf_queue(struct rockit_cfg *input_rockit_cfg)
stream->id, isprk_buf,
isprk_buf->isp_buf.buff_addr[0], isprk_buf->isp_buf.buff_addr[1]);
/* single sensor with pingpong buf, update next if need */
if (ispdev->hw_dev->is_single && !ispdev->is_suspend &&
stream->id != RKISP_STREAM_VIR &&
stream->id != RKISP_STREAM_LUMA &&
stream->streaming && !stream->next_buf) {
stream->next_buf = &isprk_buf->isp_buf;
stream->ops->update_mi(stream);
} else {
list_add_tail(&isprk_buf->isp_buf.queue, &stream->buf_queue);
}
list_add_tail(&isprk_buf->isp_buf.queue, &stream->buf_queue);
spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
return 0;

6
drivers/media/platform/rockchip/isp/rkisp.c
View File

@@ -1062,6 +1062,9 @@ void rkisp_check_idle(struct rkisp_device *dev, u32 irq)
unsigned long lock_flags = 0;
u32 val = 0;
if (!IS_HDR_RDBK(dev->rd_mode))
return;
spin_lock_irqsave(&dev->hw_dev->rdbk_lock, lock_flags);
dev->irq_ends |= (irq & dev->irq_ends_mask);
v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev,
@@ -1073,8 +1076,7 @@ void rkisp_check_idle(struct rkisp_device *dev, u32 irq)
if (!completion_done(&dev->hw_dev->monitor.cmpl))
complete(&dev->hw_dev->monitor.cmpl);
}
if ((dev->irq_ends & dev->irq_ends_mask) != dev->irq_ends_mask ||
!IS_HDR_RDBK(dev->rd_mode)) {
if ((dev->irq_ends & dev->irq_ends_mask) != dev->irq_ends_mask) {
spin_unlock_irqrestore(&dev->hw_dev->rdbk_lock, lock_flags);
return;
}

3
drivers/mfd/display-serdes/maxim/maxim-max96752.c
View File

@@ -248,6 +248,9 @@ static struct function_desc max96752_functions_desc[] = {
FUNCTION_DESC_GPIO_OUTPUT_HIGH(15),
FUNCTION_DES_DELAY_MS(10),
FUNCTION_DES_DELAY_MS(20),
FUNCTION_DES_DELAY_MS(30),
FUNCTION_DES_DELAY_MS(40),
FUNCTION_DES_DELAY_MS(50),
FUNCTION_DES_DELAY_MS(100),
FUNCTION_DES_DELAY_MS(200),

3
drivers/mfd/display-serdes/maxim/maxim-max96772.c
View File

@@ -253,6 +253,9 @@ static struct function_desc max96772_functions_desc[] = {
FUNCTION_DESC_GPIO_OUTPUT_HIGH(15),
FUNCTION_DES_DELAY_MS(10),
FUNCTION_DES_DELAY_MS(20),
FUNCTION_DES_DELAY_MS(30),
FUNCTION_DES_DELAY_MS(40),
FUNCTION_DES_DELAY_MS(50),
FUNCTION_DES_DELAY_MS(100),
FUNCTION_DES_DELAY_MS(200),

7
drivers/mfd/display-serdes/rohm/rohm-bu18rl82.c
View File

@@ -60,7 +60,7 @@ static const char *serdes_gpio_groups[] = {
.group_names = serdes_gpio_groups, \
.num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
.data = (void *)(const struct serdes_function_data []) { \
{ .gpio_rx_en = 1, .gpio_id = id + 2 } \
{ .gpio_rx_en = 1, .gpio_id = id ? (id + 2) : 0x12 } \
}, \
} \
@@ -71,7 +71,7 @@ static const char *serdes_gpio_groups[] = {
.group_names = serdes_gpio_groups, \
.num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
.data = (void *)(const struct serdes_function_data []) { \
{ .gpio_rx_en = 0, .gpio_id = id + 2 } \
{ .gpio_rx_en = 0, .gpio_id = id ? (id + 2) : 0x12 } \
}, \
} \
@@ -167,6 +167,9 @@ static struct function_desc bu18rl82_functions_desc[] = {
FUNCTION_DESC_GPIO_OUTPUT_LOW(),
FUNCTION_DES_DELAY_MS(10),
FUNCTION_DES_DELAY_MS(20),
FUNCTION_DES_DELAY_MS(30),
FUNCTION_DES_DELAY_MS(40),
FUNCTION_DES_DELAY_MS(50),
FUNCTION_DES_DELAY_MS(100),
FUNCTION_DES_DELAY_MS(200),

7
drivers/mfd/display-serdes/serdes-core.c
View File

@@ -327,13 +327,6 @@ int serdes_set_pinctrl_default(struct serdes *serdes)
{
int ret = 0;
if ((!IS_ERR(serdes->pinctrl_node)) && (!IS_ERR(serdes->pins_default))) {
ret = pinctrl_select_state(serdes->pinctrl_node, serdes->pins_default);
if (ret)
dev_err(serdes->dev, "could not set default pins\n");
SERDES_DBG_MFD("%s: name=%s default\n", __func__, dev_name(serdes->dev));
}
if ((!IS_ERR(serdes->pinctrl_node)) && (!IS_ERR(serdes->pins_init))) {
ret = pinctrl_select_state(serdes->pinctrl_node, serdes->pins_init);
if (ret)