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Merge commit '72d923c5f8afbe8f4a89eb24d44ee9f35fcbf297'

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* commit '72d923c5f8afbe8f4a89eb24d44ee9f35fcbf297':
  dt-bindings: display: rockchip: analogix-dp: Add property rockchip,disable-psr
  dt-bindings: display: rockchip: analogix-dp: Add properties for dual-channel/split modes
  dt-bindings: display: rockchip: analogix-dp: Add compatible for RK3568
  dt-bindings: display: rockchip: analogix-dp: Add support for RK3576
  UPSTREAM: dt-bindings: display: rockchip: analogix-dp: Add support for RK3588
  UPSTREAM: dt-bindings: display: rockchip: convert analogix_dp-rockchip.txt to yaml
  UPSTREAM: dt-bindings: display: bridge: convert analogix_dp.txt to yaml
  drm/rockchip: dw_hdmi: Do not enable DSC when the DSC compression ratio is below 0.375.
  media: i2c: ov13b10: add ov13b10 sensor driver
  soc: rockchip: opp_select: avoid duplicate of_find_property
  pinctrl: rockchip: Correctly support rk3308/rk3308b/rk3308bs

Change-Id: I38894eeac85dec0f182a500e2a6e3a869a566006
This commit is contained in:
Tao Huang
2025-07-28 19:27:04 +08:00
parent 9169752c68 72d923c5f8
commit 97c30bd71a
9 changed files with 1882 additions and 1336 deletions
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63
Documentation/devicetree/bindings/display/bridge/analogix,dp.yaml Normal file
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@@ -0,0 +1,63 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/analogix,dp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analogix Display Port bridge
maintainers:
- Rob Herring <robh@kernel.org>
properties:
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks: true
clock-names: true
phys: true
phy-names:
const: dp
force-hpd:
description:
Indicate driver need force hpd when hpd detect failed, this
is used for some eDP screen which don not have a hpd signal.
hpd-gpios:
description:
Hotplug detect GPIO.
Indicates which GPIO should be used for hotplug detection
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description:
Input node to receive pixel data.
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
Port node with one endpoint connected to a dp-connector node.
required:
- port@0
- port@1
required:
- reg
- interrupts
- clock-names
- clocks
- ports
additionalProperties: true

57
Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
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@@ -1,57 +0,0 @@
Analogix Display Port bridge bindings
Required properties for dp-controller:
-compatible:
platform specific such as:
* "samsung,exynos5-dp"
* "rockchip,rk3288-dp"
* "rockchip,rk3399-edp"
-reg:
physical base address of the controller and length
of memory mapped region.
-interrupts:
interrupt combiner values.
-clocks:
from common clock binding: handle to dp clock.
-clock-names:
from common clock binding: Shall be "dp".
-phys:
from general PHY binding: the phandle for the PHY device.
-phy-names:
from general PHY binding: Should be "dp".
Optional properties for dp-controller:
-analogix,video-bist-enable:
Enable video bist pattern for DP_TX debugging.
-force-hpd:
Indicate driver need force hpd when hpd detect failed, this
is used for some eDP screen which don't have hpd signal.
-hpd-gpios:
Hotplug detect GPIO.
Indicates which GPIO should be used for hotplug detection
-panel-self-test:
Enable optional LCD Panel Self Test.
-port@[X]: SoC specific port nodes with endpoint definitions as defined
in Documentation/devicetree/bindings/media/video-interfaces.txt,
please refer to the SoC specific binding document:
* Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
* Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
-support-psr:
Enable Source's PSR capability.
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
-------------------------------------------------------------------------------
Example:
dp-controller {
compatible = "samsung,exynos5-dp";
reg = <0x145b0000 0x10000>;
interrupts = <10 3>;
interrupt-parent = <&combiner>;
clocks = <&clock 342>;
clock-names = "dp";
phys = <&dp_phy>;
phy-names = "dp";
};

2
Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
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@@ -50,7 +50,7 @@ Optional properties for dp-controller:
Documentation/devicetree/bindings/display/panel/display-timing.txt
For the below properties, please refer to Analogix DP binding document:
* Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
* Documentation/devicetree/bindings/display/bridge/analogix,dp.yaml
-phys (required)
-phy-names (required)
-hpd-gpios (optional)

98
Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
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@@ -1,98 +0,0 @@
Rockchip RK3288 specific extensions to the Analogix Display Port
================================
Required properties:
- compatible: "rockchip,rk3288-dp",
"rockchip,rk3399-edp";
- reg: physical base address of the controller and length
- clocks: from common clock binding: handle to dp clock.
of memory mapped region.
- clock-names: from common clock binding:
Required elements: "dp" "pclk"
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
- pinctrl-0: pin-control mode. should be <&edp_hpd>
- reset-names: Must include the name "dp"
- rockchip,grf: this soc should set GRF regs, so need get grf here.
- ports: there are 2 port nodes with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
Port 0: contained 2 endpoints, connecting to the output of vop.
Port 1: contained 1 endpoint, connecting to the input of panel.
Optional property for different chips:
- clocks: from common clock binding: handle to grf_vio clock.
- clock-names: from common clock binding:
Required elements: "grf"
For the below properties, please refer to Analogix DP binding document:
* Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
- phys (required)
- phy-names (required)
- hpd-gpios (optional)
- force-hpd (optional)
-------------------------------------------------------------------------------
Example:
dp-controller: dp@ff970000 {
compatible = "rockchip,rk3288-dp";
reg = <0xff970000 0x4000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
clock-names = "dp", "pclk";
phys = <&dp_phy>;
phy-names = "dp";
rockchip,grf = <&grf>;
resets = <&cru 111>;
reset-names = "dp";
pinctrl-names = "default";
pinctrl-0 = <&edp_hpd>;
ports {
#address-cells = <1>;
#size-cells = <0>;
edp_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
edp_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_edp>;
};
edp_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_edp>;
};
};
edp_out: port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
edp_out_panel: endpoint {
reg = <0>;
remote-endpoint = <&panel_in_edp>
};
};
};
};
pinctrl {
edp {
edp_hpd: edp-hpd {
rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_none>;
};
};
};

171
Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml Normal file
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@@ -0,0 +1,171 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/rockchip/rockchip,analogix-dp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip specific extensions to the Analogix Display Port
maintainers:
- Sandy Huang <hjc@rock-chips.com>
- Heiko Stuebner <heiko@sntech.de>
properties:
compatible:
enum:
- rockchip,rk3288-dp
- rockchip,rk3399-edp
- rockchip,rk3568-edp
- rockchip,rk3576-edp
- rockchip,rk3588-edp
clocks:
minItems: 2
maxItems: 3
clock-names:
minItems: 2
items:
- const: dp
- const: pclk
- const: grf
power-domains:
maxItems: 1
resets:
minItems: 1
maxItems: 2
reset-names:
minItems: 1
items:
- const: dp
- const: apb
rockchip,data-swap:
description:
Indicate whether to enable data swap function for split mode or dual
channel mode. It can be helpful to deal with the reversed hardware
design issue in left and right display interfaces.
rockchip,disable-psr:
description:
Indicate whether to disable PSR function when the PSR
capability of Sink device is detected.
rockchip,dual-channel:
description:
Indicate whether to enable dual channel mode, which horizontally
splits a single video port's output to drive one displays with
identical interfaces and consistent display timing.
| | ---> | eDP0 | \ | |
| Video Port | --> | Panel |
| | ---> | eDP1 | / | |
rockchip,dual-connector-split:
description:
Indicate whether to enable dual connector split mode, which horizontally
splits a single video port's output to drive two displays with different
interfaces and consistent display timing.
| | ---> | eDP0 | ---> | | |
| Video Port | | Panel0(Left) | Panel1(right) |
| | ---> | MIPI1 | | | |
----------------------------------^
rockchip,grf:
$ref: /schemas/types.yaml#/definitions/phandle
description:
This SoC makes use of GRF regs.
rockchip,left-display:
description:
Assign the specific interface for the left display in dual connector
split mode. It can be helpful to deal with the reversed hardware
design issue in left and right display interfaces.
rockchip,split-mode:
description:
Indicate whether to enable split mode, which horizontally splits
a single video port's output to drive two displays with identical
interfaces and consistent display timing.
| | ---> | eDP0 | ---> | | |
| Video Port | | Panel0(Left) | Panel1(right) |
| | ---> | eDP1 | | | |
---------------------------------^
required:
- compatible
- clocks
- clock-names
- resets
- reset-names
- rockchip,grf
allOf:
- $ref: /schemas/display/bridge/analogix,dp.yaml#
- if:
properties:
compatible:
contains:
enum:
- rockchip,rk3568-edp
- rockchip,rk3576-edp
- rockchip,rk3588-edp
then:
properties:
resets:
minItems: 2
reset-names:
minItems: 2
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/rk3288-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
dp@ff970000 {
compatible = "rockchip,rk3288-dp";
reg = <0xff970000 0x4000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
clock-names = "dp", "pclk";
phys = <&dp_phy>;
phy-names = "dp";
resets = <&cru 111>;
reset-names = "dp";
rockchip,grf = <&grf>;
pinctrl-0 = <&edp_hpd>;
pinctrl-names = "default";
ports {
#address-cells = <1>;
#size-cells = <0>;
edp_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
edp_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_edp>;
};
edp_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_edp>;
};
};
edp_out: port@1 {
reg = <1>;
edp_out_panel: endpoint {
remote-endpoint = <&panel_in_edp>;
};
};
};
};

41
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
View File

@@ -1036,23 +1036,36 @@ rockchip_hdmi_find_by_id(struct device_driver *drv, unsigned int id)
return dev_get_drvdata(dev);
}
static bool rockchip_hdmi_check_dsc_rate_supported(struct rockchip_hdmi *hdmi,
u64 tmdsclk, u8 bpp)
{
u64 data_rate, dsc_rate;
u64 frl_rate, dsc_frl_rate;
frl_rate = (u64)hdmi->hdmi21_data.max_lanes *
hdmi->hdmi21_data.max_frl_rate_per_lane * 1000000000;
dsc_frl_rate = (u64)hdmi->hdmi21_data.dsc_cap.max_lanes *
hdmi->hdmi21_data.dsc_cap.max_frl_rate_per_lane * 1000000000;
data_rate = (u64)tmdsclk * bpp;
data_rate = DIV_ROUND_UP_ULL(data_rate * 18, 16);
/* compression ratio needs to be greater than 0.375. */
dsc_rate = DIV_ROUND_UP_ULL(data_rate * 9, 24);
if ((data_rate > frl_rate) && (dsc_rate > dsc_frl_rate))
return true;
return false;
}
static bool rockchip_hdmi_if_dsc_enable(struct rockchip_hdmi *hdmi, unsigned int tmdsclk)
{
u64 data_rate;
u64 frl_rate = (u64)hdmi->link_cfg.frl_lanes * hdmi->link_cfg.rate_per_lane * 1000000;
u8 bpp = hdmi_bus_fmt_color_depth(hdmi->bus_format) * 3;
/* rk3588 dsc can't support yuv420/422 dsc */
if (hdmi_bus_fmt_is_yuv420(hdmi->bus_format) || hdmi_bus_fmt_is_yuv422(hdmi->bus_format))
return false;
data_rate = (u64)tmdsclk * bpp;
data_rate = DIV_ROUND_UP_ULL(data_rate * 18, 16);
if (data_rate > frl_rate)
return true;
return false;
return rockchip_hdmi_check_dsc_rate_supported(hdmi, tmdsclk, bpp);
}
static void hdmi_select_link_config(struct rockchip_hdmi *hdmi,
@@ -1092,7 +1105,7 @@ static void hdmi_select_link_config(struct rockchip_hdmi *hdmi,
max_dsc_rate_per_lane =
hdmi->hdmi21_data.dsc_cap.max_frl_rate_per_lane;
if (rockchip_hdmi_if_dsc_enable(hdmi, tmdsclk)) {
if (rockchip_hdmi_if_dsc_enable(hdmi, tmdsclk * 1000)) {
hdmi->link_cfg.dsc_mode = true;
hdmi->link_cfg.frl_lanes = max_dsc_lanes;
hdmi->link_cfg.rate_per_lane = max_dsc_rate_per_lane;
@@ -2419,6 +2432,7 @@ dw_hdmi_rockchip_select_output(struct drm_connector_state *conn_state,
bool support_dc = false;
bool sink_is_hdmi = true;
bool yuv422_out = false;
bool dsc_rate_supported;
u32 max_tmds_clock = info->max_tmds_clock;
int output_eotf;
@@ -2537,9 +2551,14 @@ dw_hdmi_rockchip_select_output(struct drm_connector_state *conn_state,
DRM_MODE_FLAG_3D_FRAME_PACKING)
pixclock *= 2;
tmdsclock = hdmi_get_tmdsclock(hdmi, mode.clock * 1000);
dsc_rate_supported =
rockchip_hdmi_check_dsc_rate_supported(hdmi, tmdsclock, color_depth * 3);
if (drm_mode_is_420_only(info, &mode) ||
(hdmi->is_hdmi_qp && mode.clock > 1188000 &&
(*color_format == RK_IF_FORMAT_YCBCR422 || hdmi->force_disable_dsc)))
(*color_format == RK_IF_FORMAT_YCBCR422 || hdmi->force_disable_dsc ||
!dsc_rate_supported)))
*color_format = RK_IF_FORMAT_YCBCR420;
if (!sink_is_hdmi) {

2669
drivers/media/i2c/ov13b10.c
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File diff suppressed because it is too large Load Diff

111
drivers/pinctrl/pinctrl-rockchip.c
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@@ -615,6 +615,80 @@ static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
};
static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
{
/* gpio1b6_sel */
.num = 1,
.pin = 14,
.reg = 0x28,
.bit = 12,
.mask = 0xf
}, {
/* gpio1b7_sel */
.num = 1,
.pin = 15,
.reg = 0x2c,
.bit = 0,
.mask = 0x3
}, {
/* gpio1c2_sel */
.num = 1,
.pin = 18,
.reg = 0x30,
.bit = 4,
.mask = 0xf
}, {
/* gpio1c3_sel */
.num = 1,
.pin = 19,
.reg = 0x30,
.bit = 8,
.mask = 0xf
}, {
/* gpio1c4_sel */
.num = 1,
.pin = 20,
.reg = 0x30,
.bit = 12,
.mask = 0xf
}, {
/* gpio1c5_sel */
.num = 1,
.pin = 21,
.reg = 0x34,
.bit = 0,
.mask = 0xf
}, {
/* gpio1c6_sel */
.num = 1,
.pin = 22,
.reg = 0x34,
.bit = 4,
.mask = 0xf
}, {
/* gpio1c7_sel */
.num = 1,
.pin = 23,
.reg = 0x34,
.bit = 8,
.mask = 0xf
}, {
/* gpio3b4_sel */
.num = 3,
.pin = 12,
.reg = 0x68,
.bit = 8,
.mask = 0xf
}, {
/* gpio3b5_sel */
.num = 3,
.pin = 13,
.reg = 0x68,
.bit = 12,
.mask = 0xf
},
};
static struct rockchip_mux_recalced_data rk3308b_mux_recalced_data[] = {
{
/* gpio1b6_sel */
.num = 1,
@@ -1001,6 +1075,35 @@ static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
};
static struct rockchip_mux_route_data rk3308b_mux_route_data[] = {
RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */
RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */
RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */
RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */
RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */
RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */
RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */
RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */
RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */
RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */
RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */
RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */
RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */
RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */
RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */
RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */
RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */
RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */
RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */
RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */
};
static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */
RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */
@@ -4853,6 +4956,12 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
match = of_match_node(rockchip_pinctrl_dt_match, node);
ctrl = (struct rockchip_pin_ctrl *)match->data;
if (IS_ENABLED(CONFIG_CPU_RK3308) && (soc_is_rk3308b() || soc_is_rk3308bs())) {
ctrl->iomux_recalced = rk3308b_mux_recalced_data;
ctrl->niomux_recalced = ARRAY_SIZE(rk3308b_mux_recalced_data);
ctrl->iomux_routes = rk3308b_mux_route_data;
ctrl->niomux_routes = ARRAY_SIZE(rk3308b_mux_route_data);
}
if (IS_ENABLED(CONFIG_CPU_RK3308) && soc_is_rk3308bs())
ctrl->pin_banks = rk3308bs_pin_banks;
if (IS_ENABLED(CONFIG_CPU_PX30) && soc_is_px30s())
@@ -5117,7 +5226,7 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
/* try to find the optional reference to the rmio syscon */
info->regmap_rmio = syscon_regmap_lookup_by_phandle_optional(np, "rockchip,rmio");
if (IS_ENABLED(CONFIG_CPU_RK3308) && ctrl->type == RK3308) {
if (IS_ENABLED(CONFIG_CPU_RK3308) && (soc_is_rk3308b() || soc_is_rk3308bs())) {
ret = rk3308_soc_data_init(info);
if (ret)
return ret;

6
drivers/soc/rockchip/rockchip_opp_select.c
View File

@@ -1411,10 +1411,10 @@ static void rockchip_init_pvtpll_table(struct device *dev,
"rockchip,pvtpll-table-B%d", info->bin);
prop = of_find_property(np, prop_name, NULL);
}
if (!prop)
if (!prop) {
sprintf(prop_name, "rockchip,pvtpll-table");
prop = of_find_property(np, prop_name, NULL);
prop = of_find_property(np, prop_name, NULL);
}
if (!prop)
goto out;