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clk: rockchip: using unify parameters for ddr frequency scanning.

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Change-Id: Ibd3befd3cd674af263402f6984ee6d605eb087c8
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Tang Yun ping
2017-05-16 20:11:32 +08:00
committed by Tao Huang
parent 5145b181c8
commit 982114c422
1 changed files with 11 additions and 14 deletions
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25
drivers/clk/rockchip/clk-ddr.c
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@@ -197,8 +197,13 @@ static const struct clk_ops rockchip_ddrclk_scpi_ops = {
.get_parent = rockchip_ddrclk_get_parent,
};
struct set_rate_params {
struct share_params {
u32 hz;
u32 lcdc_type;
u32 vop;
u32 vop_dclk_mode;
u32 sr_idle_en;
u32 addr_mcu_el3;
/*
* 1: need to wait flag1
* 0: never wait flag1
@@ -209,15 +214,7 @@ struct set_rate_params {
* 0: never wait flag1
*/
u32 wait_flag0;
/* these parameters, not use in RK322xh */
u32 lcdc_type;
u32 vop;
/* if need, add parameter after */
};
struct round_rate_params {
u32 hz;
/* if need, add parameter after */
/* if need, add parameter after */
};
struct rockchip_ddrclk_data {
@@ -243,13 +240,13 @@ static int rockchip_ddrclk_sip_set_rate_v2(struct clk_hw *hw,
unsigned long drate,
unsigned long prate)
{
struct set_rate_params *p;
struct share_params *p;
struct arm_smccc_res res;
if (!ddr_data.inited_flag)
rockchip_ddrclk_data_init();
p = (struct set_rate_params *)ddr_data.share_memory;
p = (struct share_params *)ddr_data.share_memory;
p->hz = drate;
p->lcdc_type = rk_drm_get_lcdc_type();
@@ -277,13 +274,13 @@ static long rockchip_ddrclk_sip_round_rate_v2(struct clk_hw *hw,
unsigned long rate,
unsigned long *prate)
{
struct round_rate_params *p;
struct share_params *p;
struct arm_smccc_res res;
if (!ddr_data.inited_flag)
rockchip_ddrclk_data_init();
p = (struct round_rate_params *)ddr_data.share_memory;
p = (struct share_params *)ddr_data.share_memory;
p->hz = rate;