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UPSTREAM: coresight: trbe: Unify the enabling sequence

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Unify the sequence of enabling the TRBE. We do this from
event_start and also from the TRBE IRQ handler. Lets move
this to a common helper. The only minor functional change
is returning an error when we fail to enable the TRBE.
This should be handled already.

Since we now have unique entry point to trying to enable TRBE,
move the format flag setting to the central place.

Bug: 213931796
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Leo Yan <leo.yan@linaro.org>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20210914102641.1852544-9-suzuki.poulose@arm.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
(cherry picked from commit 04a37a174e)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: Ic477a920ff7f8c646ea080cde22f96e185b62d68
This commit is contained in:
Suzuki K Poulose
2021-09-14 11:26:39 +01:00
committed by Todd Kjos
parent 3e0492f703
commit 984ff5cb73
1 changed files with 18 additions and 19 deletions
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37
drivers/hwtracing/coresight/coresight-trbe.c
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@@ -629,6 +629,21 @@ done:
return size;
}
static int __arm_trbe_enable(struct trbe_buf *buf,
struct perf_output_handle *handle)
{
perf_aux_output_flag(handle, PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW);
buf->trbe_limit = compute_trbe_buffer_limit(handle);
buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
if (buf->trbe_limit == buf->trbe_base) {
trbe_stop_and_truncate_event(handle);
return -ENOSPC;
}
*this_cpu_ptr(buf->cpudata->drvdata->handle) = handle;
trbe_enable_hw(buf);
return 0;
}
static int arm_trbe_enable(struct coresight_device *csdev, u32 mode, void *data)
{
struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
@@ -641,19 +656,11 @@ static int arm_trbe_enable(struct coresight_device *csdev, u32 mode, void *data)
if (mode != CS_MODE_PERF)
return -EINVAL;
perf_aux_output_flag(handle, PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW);
*this_cpu_ptr(drvdata->handle) = handle;
cpudata->buf = buf;
cpudata->mode = mode;
buf->cpudata = cpudata;
buf->trbe_limit = compute_trbe_buffer_limit(handle);
buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
if (buf->trbe_limit == buf->trbe_base) {
trbe_stop_and_truncate_event(handle);
return 0;
}
trbe_enable_hw(buf);
return 0;
return __arm_trbe_enable(buf, handle);
}
static int arm_trbe_disable(struct coresight_device *csdev)
@@ -723,15 +730,7 @@ static void trbe_handle_overflow(struct perf_output_handle *handle)
*this_cpu_ptr(buf->cpudata->drvdata->handle) = NULL;
return;
}
perf_aux_output_flag(handle, PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW);
buf->trbe_limit = compute_trbe_buffer_limit(handle);
buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
if (buf->trbe_limit == buf->trbe_base) {
trbe_stop_and_truncate_event(handle);
return;
}
*this_cpu_ptr(buf->cpudata->drvdata->handle) = handle;
trbe_enable_hw(buf);
__arm_trbe_enable(buf, handle);
}
static bool is_perf_trbe(struct perf_output_handle *handle)