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Merge commit 'bb4832d4dc32476eac184ee48b1c05572a01bc8a'

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* commit 'bb4832d4dc32476eac184ee48b1c05572a01bc8a':
  media: i2c: rk628: post process add yuv2020 to rgb
  ASoC: rk312x: Remove unused code
  media: rockchip: vicap fixes error of parse data type
  PM / devfreq: rockchip_dmc: Use new api to adjust opp table for rk3528
  arm64: dts: rockchip: rk3528: Add 324MHz and 666MHz for dmc
  ASoC: es8323: Fix power consumption

Change-Id: Ia776f4db082c8f6713993b0a67f89aa569d93672
This commit is contained in:
Tao Huang
2025-02-20 20:53:24 +08:00
parent 2c82a2c6fc bb4832d4dc
commit 98ca2198f5
6 changed files with 56 additions and 56 deletions
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8
arch/arm64/boot/dts/rockchip/rk3528.dtsi
View File

@@ -405,6 +405,14 @@
29 254 4
>;
opp-324000000 {
opp-hz = /bits/ 64 <324000000>;
opp-microvolt = <850000 850000 1000000>;
};
opp-666000000 {
opp-hz = /bits/ 64 <666000000>;
opp-microvolt = <850000 850000 1000000>;
};
opp-920000000 {
opp-hz = /bits/ 64 <920000000>;
opp-microvolt = <850000 850000 1000000>;

2
drivers/devfreq/rockchip_dmc.c
View File

@@ -1849,7 +1849,7 @@ static __maybe_unused int rk3528_dmc_init(struct platform_device *pdev,
return -ENOMEM;
}
ret = rockchip_get_freq_info(dmcfreq);
ret = rockchip_dmcfreq_adjust_opp_table(dmcfreq);
if (ret < 0) {
dev_err(&pdev->dev, "cannot get frequency info\n");
return ret;

39
drivers/media/i2c/rk628/rk628_post_process.c
View File

@@ -80,6 +80,8 @@ enum rk_pq_csc_mode {
RK_PQ_CSC_RGBL2RGBL, /* RGB LIMIT->RGB LIMIT */
RK_PQ_CSC_RGB2RGB, /* RGB FULL->RGB FULL */
RK_PQ_CSC_YUV2RGB_2020, /* YUV 2020 FULL->RGB 2020 FULL */
RK_PQ_CSC_YUV2RGB_2020_LIMIT2FULL, /* YUV 2020 LIMIT->RGB 2020 FULL */
RK_PQ_CSC_YUV2RGB_2020_LIMIT, /* YUV 2020 LIMIT->RGB 2020 LIMIT */
RK_PQ_CSC_RGB2YUV2020_LIMIT2FULL, /* BT2020RGBLIMIT -> BT2020YUVFULL */
RK_PQ_CSC_RGB2YUV2020_LIMIT, /* BT2020RGBLIMIT -> BT2020YUVLIMIT */
RK_PQ_CSC_RGB2YUV2020_FULL2LIMIT, /* BT2020RGBFULL -> BT2020YUVLIMIT */
@@ -713,6 +715,27 @@ static const struct rk_pq_csc_dc_coef rk_dc_csc_table_adobe_yuv_limit_to_yuv_lim
-64, -512, -512,
64, 512, 512
};
// 2020 YUV LIMIT -> RGB FULL
static const struct rk_pq_csc_coef rk_csc_table_identity_yuv_limit_to_rgb_full_2020 = {
1196, 0, 1724,
1196, -192, -668,
1196, 2200, 0,
};
static const struct rk_pq_csc_dc_coef rk_dc_csc_table_identity_yuv_limit_to_rgb_full_2020 = {
-64, -512, -512,
0, 0, 0
};
// 2020 YUV LIMIT -> RGB LIMIT
static const struct rk_pq_csc_coef rk_csc_table_identity_yuv_limit_to_rgb_limit_2020 = {
1024, 0, 1476,
1024, -165, -572,
1024, 1884, 0,
};
static const struct rk_pq_csc_dc_coef rk_dc_csc_table_identity_yuv_limit_to_rgb_limit_2020 = {
-64, -512, -512,
64, 64, 64
};
/*
*CSC Param Struct
*/
@@ -981,6 +1004,22 @@ static const struct rk_csc_mode_coef g_mode_csc_coef[] = {
OPTM_CS_E_XV_YCC_2020, OPTM_CS_E_RGB_2020, true, true
}
},
{
RK_PQ_CSC_YUV2RGB_2020_LIMIT2FULL, "YUV2020 L->RGB2020 F",
&rk_csc_table_identity_yuv_limit_to_rgb_full_2020,
&rk_dc_csc_table_identity_yuv_limit_to_rgb_full_2020,
{
OPTM_CS_E_XV_YCC_2020, OPTM_CS_E_RGB_2020, false, true
}
},
{
RK_PQ_CSC_YUV2RGB_2020_LIMIT, "YUV2020 L->RGB2020 L",
&rk_csc_table_identity_yuv_limit_to_rgb_limit_2020,
&rk_dc_csc_table_identity_yuv_limit_to_rgb_limit_2020,
{
OPTM_CS_E_XV_YCC_2020, OPTM_CS_E_RGB_2020, false, false
}
},
{
RK_PQ_CSC_RGB2YUV2020_LIMIT2FULL, "RGB2020 L->YUV2020 F",
&rk_csc_table_identity_rgb_limit_to_yuv_full_2020,

7
drivers/media/platform/rockchip/cif/capture.c
View File

@@ -4422,11 +4422,12 @@ static void rkcif_modify_frame_skip_config(struct rkcif_stream *stream)
}
}
static u32 rkcif_get_parse_type_rk3576(const struct cif_input_fmt *cif_fmt_in)
static u32 rkcif_get_parse_type_rk3576(const struct cif_input_fmt *cif_fmt_in,
struct csi_channel_info *channel)
{
u32 parse_type = 0;
switch (cif_fmt_in->csi_fmt_val) {
switch (channel->csi_fmt_val) {
case CSI_WRDDR_TYPE_RAW8:
parse_type = CSI_WRDDR_TYPE_RAW8 << 3;
break;
@@ -4701,7 +4702,7 @@ static int rkcif_csi_channel_set_v1(struct rkcif_stream *stream,
if (dev->chip_id > CHIP_RK3562_CIF) {
val = CSI_ENABLE_CAPTURE | dma_en |
CSI_ENABLE_CROP_RK3576;
val |= rkcif_get_parse_type_rk3576(stream->cif_fmt_in);
val |= rkcif_get_parse_type_rk3576(stream->cif_fmt_in, channel);
val |= rkcif_csi_get_output_type_mask_rk3576(stream);
val |= stream->cif_fmt_in->csi_yuv_order >> 4;
if (stream->is_high_align)

5
sound/soc/codecs/es8323.c
View File

@@ -755,6 +755,9 @@ static int es8323_resume(struct snd_soc_component *component)
snd_soc_component_write(component, 0x31, es8323_DEF_VOL);
snd_soc_component_write(component, 0x30, es8323_DEF_VOL);
snd_soc_component_write(component, 0x19, 0x02);
es8323_set_bias_level(component, SND_SOC_BIAS_OFF);
return 0;
}
@@ -818,7 +821,7 @@ static int es8323_probe(struct snd_soc_component *component)
usleep_range(18000, 20000);
snd_soc_component_write(component, 0x04, 0x3C);
es8323_set_bias_level(component, SND_SOC_BIAS_STANDBY);
es8323_set_bias_level(component, SND_SOC_BIAS_OFF);
return 0;
}

51
sound/soc/codecs/rk312x_codec.c
View File

@@ -94,10 +94,6 @@ struct rk312x_codec_priv {
struct gpio_desc *hp_ctl_gpio;
int spk_mute_delay;
int hp_mute_delay;
int spk_hp_switch_gpio;
/* 1 spk; */
/* 0 hp; */
enum of_gpio_flags spk_io;
/* 0 for box; */
/* 1 default for mid; */
@@ -275,30 +271,6 @@ static int rk312x_codec_ctl_gpio(int gpio, int level)
return 0;
}
#if 0
static int switch_to_spk(int enable)
{
if (!rk312x_priv) {
DBG(KERN_ERR"%s : rk312x is NULL\n", __func__);
return -EINVAL;
}
if (enable) {
if (rk312x_priv->spk_hp_switch_gpio != INVALID_GPIO) {
gpio_set_value(rk312x_priv->spk_hp_switch_gpio, rk312x_priv->spk_io);
DBG(KERN_INFO"%s switch to spk\n", __func__);
msleep(rk312x_priv->spk_mute_delay);
}
} else {
if (rk312x_priv->spk_hp_switch_gpio != INVALID_GPIO) {
gpio_set_value(rk312x_priv->spk_hp_switch_gpio, !rk312x_priv->spk_io);
DBG(KERN_INFO"%s switch to hp\n", __func__);
msleep(rk312x_priv->hp_mute_delay);
}
}
return 0;
}
#endif
static int rk312x_reset(struct snd_soc_component *component)
{
DBG("%s\n", __func__);
@@ -2292,29 +2264,6 @@ static int rk312x_platform_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, rk312x);
rk312x->dev = &pdev->dev;
#if 0
rk312x->spk_hp_switch_gpio = of_get_named_gpio_flags(rk312x_np,
"spk_hp_switch_gpio", 0, &rk312x->spk_io);
rk312x->spk_io = !rk312x->spk_io;
if (!gpio_is_valid(rk312x->spk_hp_switch_gpio)) {
dbg_codec(2, "invalid spk hp switch_gpio : %d\n",
rk312x->spk_hp_switch_gpio);
rk312x->spk_hp_switch_gpio = INVALID_GPIO;
/* ret = -ENOENT; */
/* goto err__; */
}
DBG("%s : spk_hp_switch_gpio %d spk active_level %d \n", __func__,
rk312x->spk_hp_switch_gpio, rk312x->spk_io);
if(rk312x->spk_hp_switch_gpio != INVALID_GPIO) {
ret = devm_gpio_request(&pdev->dev, rk312x->spk_hp_switch_gpio, "spk_hp_switch");
if (ret < 0) {
dbg_codec(2, "rk312x_platform_probe spk_hp_switch_gpio fail\n");
/* goto err__; */
rk312x->spk_hp_switch_gpio = INVALID_GPIO;
}
}
#endif
rk312x->edev = devm_extcon_dev_allocate(&pdev->dev, headset_extcon_cable);
if (IS_ERR(rk312x->edev)) {
dev_err(&pdev->dev, "failed to allocate extcon device\n");