rk3368: clk: modify relation in software of clocks under PD_VIO

It is necessary to enable hclk_vio_h2p\pclk_vio_h2p\hclk_vio_ahb_arbi
for devices under power doamin PD_VIO wen they work. Thus these clks
are modified to be parent of other clks from hclk_vio.

Signed-off-by: dkl <dkl@rock-chips.com>
This commit is contained in:
dkl
2015-03-09 11:39:59 +08:00
parent 75ce2b9330
commit 98d0d65e06

View File

@@ -2432,9 +2432,9 @@
<&clk_gates16 9>, <&clk_gates16 8>,
<&clk_gates16 9>, <&clk_gates16 9>,
<&clk_gates16 8>, <&clk_gates16 8>,
<&clk_gates16 8>, <&clk_gates17 8>,
<&hclk_vio>, <&aclk_vio0>,
<&clk_gates16 7>, <&aclk_vio0>,
<&aclk_rga_pre>, <&clk_gates16 9>,
<&clk_gates16 8>, <&pclkin_vip>,
@@ -2464,9 +2464,9 @@
<&pclkin_isp>, <&pclk_vio>,
<&pclk_vio>, <&dummy>,
<&pclk_vio>, <&clk_gates16 8>,
<&pclk_vio>, <&hclk_vio>,
<&pclk_vio>, <&pclk_vio>,
<&clk_gates17 7>, <&pclk_vio>,
<&clk_gates16 10>, <&pclk_vio>,
<&clk_gates16 8>, <&dummy>,