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Merge commit 'a1d62b81aec54ac9382ba495ad6803a12e83cb30'

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* commit 'a1d62b81aec54ac9382ba495ad6803a12e83cb30':
  pwm: rockchip: Remove redundant pwmchip_remove()
  phy: rockchip: inno-hdmi: Support automatic calculation of the phy pll frequency division coefficient
  arm64: configs: rockchip_linux_defconfig enable CONFIG_PCIE_FUNC_RKEP
  PCI: rockchip: dw: Add PCIE_DW_ROCKCHIP_RC_DMATEST macro limit for dma test
  phy: rockchip-snps-pcie3: increase sram init timeout
  Revert "arm64: dts: rockchip: rv1126b-evb2-v10-tb-400w: Add rndis support"
  spi: spi-rockchip-sfc: prefer asynchronous probing when CONFIG_ROCKCHIP_THUNDER_BOOT=y
  dmaengine: pl330: Fix NULL pointer dereference in pl330_tasklet()
  drm/rockchip: drv: use drm_format_info_bpp() to get bpp
  soc: rockchip: rockchip_thunderboot_mmc: Don't continue if timeout happens when loading firmware
  power: supply: rk817_battery: Optimize temperature filtering functionality
  power: supply: rk817_battery: Support rk817b
  power: supply: rk817_battery: Implement temperature filtering functionality
  power: supply: rk817_battery: Smooth charging/discharging curves
  power: supply: rk817_battery: Resolve data overflow issue
  power: supply: rk817_battery: Add auto-stage switching for TS crossflow
  power: supply: rk817_battery: Consider the effect of contact resistance

Change-Id: Ia63199dbc6243fd479748a507737abecf4e0278f
This commit is contained in:
Tao Huang
2025-07-09 19:18:22 +08:00
parent ef5682f1c4 a1d62b81ae
commit 98d4dd654b
13 changed files with 806 additions and 238 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
arch/arm64/boot/dts/rockchip/rv1126b-evb2-v10-tb-400w.dts
View File

@@ -65,19 +65,3 @@
*/
reg = <0x41320000 0x14c8000>;
};
&usb2phy {
status = "okay";
};
&usb2phy_otg {
status = "okay";
};
&usb3phy {
status = "okay";
};
&usb_drd_dwc3 {
status = "okay";
};

1
arch/arm64/configs/rockchip_linux_defconfig
View File

@@ -158,6 +158,7 @@ CONFIG_BLK_DEV_RAM_COUNT=1
CONFIG_BLK_DEV_NVME=y
CONFIG_RK628_MISC=y
CONFIG_RK628_MISC_HDMITX=y
CONFIG_PCIE_FUNC_RKEP=y
CONFIG_SRAM=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_DEV_SR=y

5
drivers/dma/pl330.c
View File

@@ -2280,6 +2280,11 @@ static void pl330_tasklet(struct tasklet_struct *t)
spin_lock_irqsave(&pch->lock, flags);
if (!pch->thread) {
spin_unlock_irqrestore(&pch->lock, flags);
return;
}
/* Pick up ripe tomatoes */
list_for_each_entry_safe(desc, _dt, &pch->work_list, node) {
if (desc->status == DONE) {

9
drivers/gpu/drm/rockchip/rockchip_drm_drv.c
View File

@@ -291,10 +291,6 @@ EXPORT_SYMBOL(drm_mode_convert_to_origin_mode);
uint32_t rockchip_drm_get_bpp(const struct drm_format_info *info)
{
/* use whatever a driver has set */
if (info->cpp[0])
return info->cpp[0] * 8;
switch (info->format) {
case DRM_FORMAT_YUV420_8BIT:
return 12;
@@ -303,11 +299,8 @@ uint32_t rockchip_drm_get_bpp(const struct drm_format_info *info)
case DRM_FORMAT_VUY101010:
return 30;
default:
break;
return drm_format_info_bpp(info, 0);
}
/* all attempts failed */
return 0;
}
EXPORT_SYMBOL(rockchip_drm_get_bpp);

20
drivers/pci/controller/dwc/Kconfig
View File

@@ -97,13 +97,6 @@ config PCIE_RK_THREADED_INIT
help
Enables threaded initialize Rockchip DW based PCIe controller.
config PCIE_DW_DMATEST
bool "DesignWare PCIe DMA test"
depends on PCIE_DW_ROCKCHIP
depends on !ROCKCHIP_PCIE_DMA_OBJ
help
Enables support for the DW PCIe controller DMA test.
config PCIE_DW_ROCKCHIP_EP
bool "Rockchip DesignWare PCIe EP controller"
select PCIE_DW
@@ -112,6 +105,19 @@ config PCIE_DW_ROCKCHIP_EP
help
Enables support for the DW PCIe controller in the Rockchip SoC.
config PCIE_DW_DMATEST
bool "DesignWare PCIe DMA test"
depends on (PCIE_DW_ROCKCHIP || PCIE_DW_ROCKCHIP_EP || PCIE_FUNC_RKEP)
depends on !ROCKCHIP_PCIE_DMA_OBJ
help
Enables support for the DW PCIe controller DMA test.
config PCIE_DW_ROCKCHIP_RC_DMATEST
bool "DesignWare PCIe Rockchip RC Enable DMA test"
depends on PCIE_DW_DMATEST
help
Enables support for the DW PCIe controller DMA test in the Rockchip SoC.
config PCI_EXYNOS
tristate "Samsung Exynos PCIe controller"
depends on ARCH_EXYNOS || COMPILE_TEST

7
drivers/pci/controller/dwc/pcie-dw-rockchip.c
View File

@@ -573,13 +573,16 @@ static int rk_pcie_init_dma_trx(struct rk_pcie *rk_pcie)
if (!rk_pcie_udma_enabled(rk_pcie))
return 0;
#ifdef PCIE_DW_ROCKCHIP_RC_DMATEST
rk_pcie->dma_obj = pcie_dw_dmatest_register(rk_pcie->pci->dev, true);
if (IS_ERR(rk_pcie->dma_obj)) {
dev_err(rk_pcie->pci->dev, "failed to prepare dmatest\n");
return -EINVAL;
} else if (!rk_pcie->dma_obj) { /* !CONFIG_ROCKCHIP_PCIE_DMA_OBJ */
return 0;
}
#endif
if (!rk_pcie->dma_obj)
return 0;
/* Enable client write and read interrupt */
rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_INTR_MASK, 0xc000000);

275
drivers/phy/rockchip/phy-rockchip-inno-hdmi-phy.c
View File

@@ -476,6 +476,243 @@ static irqreturn_t inno_hdmi_phy_irq(int irq, void *dev_id)
return IRQ_HANDLED;
}
#define FREF 24000000
#define FFBD_FRAC_MAX 16777216
static int inno_hdmi_phy_pll_cal(struct inno_hdmi_phy *inno, struct pre_pll_config *cfg,
u64 pixelclk, u64 tmdsclock)
{
u32 j, k, i, nf = 0, nr = 1, tmds_no, tmds_a, tmds_b, tmds_c;
u32 pclk_no = 0, prepclk_no = 0, div_5 = 0;
u8 tmdsa[4] = {1, 2, 3, 5};
u8 tmdsbc[4] = {1, 2, 4, 8};
u8 pclkb[4] = {2, 3, 4, 5};
u8 pclkc[4] = {1, 2, 4, 8};
u32 pclka, pclkd;
u32 rem = 0;
u64 frac_div = 0;
u64 fvco;
u64 frefdiv;
bool frac_supported = true;
bool frac_cal = false;
dev_dbg(inno->dev, "pixelclk:%llu,tmdsclock:%llu\n", pixelclk, tmdsclock);
if (pixelclk > tmdsclock && pixelclk < 340000000) {
dev_dbg(inno->dev, "hdmi1.4 resolution can't support yuv420 mode\n");
return 0;
}
if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228)
frac_supported = false;
/* VCO frequency shall not be higher than 3.2Ghz */
i = DIV_ROUND_UP_ULL(3200000000ULL, tmdsclock * 4);
continue_cal:
/*
* If the current parameters can not get the correct clock,
* return here and continue to calculate with next set of
* parameters until the allowed range is exceeded or get
* the correct clock.
*/
for (; nr < 31; nr++) {
frefdiv = FREF / nr;
nf = 0;
/* VCO frequency shall not be lower than 1.4Ghz */
while (((tmdsclock * 4 * --i) > 1400000000ULL) && i > 0) {
fvco = tmdsclock * 4 * i;
div_5 = 0;
div_u64_rem(fvco, frefdiv, &rem);
dev_dbg(inno->dev, "i:%u rem:%u frefdiv:%llu fvco:%llu\n",
i, rem, frefdiv, fvco);
/* fvco = (fref / nr) * nf */
if (!frac_cal && !rem && (div_u64(fvco, frefdiv) <= 4096)) {
nf = div_u64(fvco, frefdiv);
tmds_no = i;
break;
/* fvco = (fref / nr) * (nf + frac_div / 2^24) */
} else if (frac_cal && (div_u64(fvco, frefdiv) <= 4096)) {
nf = div_u64(fvco, frefdiv);
tmds_no = i;
frac_div = (u64)rem * FFBD_FRAC_MAX;
frac_div = div_u64(frac_div, frefdiv);
dev_dbg(inno->dev, "frac_div:%llu\n", frac_div);
break;
}
}
if (nf)
break;
i = DIV_ROUND_UP_ULL(3200000000ULL, tmdsclock * 4);
}
if (nr == 31) {
if (frac_supported) {
/*
* RK3528/RK3328 support fraction calculation. If this clk can't
* be calculated with integers, using fraction to
* calculate.
*/
if (!frac_cal) {
frac_cal = 1;
nr = 1;
goto continue_cal;
}
}
dev_dbg(inno->dev, "can't support tmdsclock:%llu\n", tmdsclock);
return 0;
}
if (tmdsclock > 340000000) {
for (k = 0; k < 4; k++) {
/*
* HDMI2.0 is 1/40 mode, tmds lane clk is 1/4 pixel clk.
* so f_linkclk must be four times that of f_tmdsclk,
* tmds_divb must be four times that of tmds_divc.
* The cycle starts from tmdsbc[2].
*/
for (j = 2; j < 4; j++) {
if (tmdsa[k] * tmdsbc[j] == (4 * tmds_no))
break;
}
if (j < 4)
break;
}
} else {
for (k = 0; k < 4; k++) {
for (j = 0; j < 4; j++) {
if (tmdsa[k] * tmdsbc[j] == tmds_no)
break;
}
if (j < 4)
break;
}
}
if (k == 4) {
nf = 0;
goto continue_cal;
}
tmds_a = k;
tmds_b = j;
if (tmdsclock > 340000000)
tmds_c = j - 2;
else
tmds_c = j;
dev_dbg(inno->dev, "tmds_a %d (%d) tmds_b %d (%d) tmds_c %d (%d)\n",
tmds_a, tmdsa[tmds_a], tmds_b, tmdsbc[tmds_b], tmds_c,
tmdsbc[tmds_c]);
/* In yuv420 mode f_pclk is twice of f_prepclk */
if (pixelclk > tmdsclock) {
div_u64_rem(fvco * 2, pixelclk, &rem);
if (rem)
goto continue_cal;
prepclk_no = div_u64(fvco * 2, pixelclk);
if (div_u64(fvco, pixelclk) == 5) {
div_5 = 1;
} else {
if (prepclk_no % 4)
goto continue_cal;
pclk_no = prepclk_no / 4;
}
} else {
div_u64_rem(fvco, pixelclk, &rem);
if (rem)
goto continue_cal;
prepclk_no = div_u64(fvco, pixelclk);
if (div_u64(fvco, pixelclk) == 5) {
div_5 = 1;
} else {
if (prepclk_no % 2)
goto continue_cal;
pclk_no = prepclk_no / 2;
}
}
dev_dbg(inno->dev, "prepclk_no:%d,pclk_no:%d,div_5:%d\n",
prepclk_no, pclk_no, div_5);
for (k = 0; k < 4; k++) {
for (j = 0; j < 4; j++) {
if (pclkb[k] * pclkc[j] == prepclk_no)
break;
}
if (j < 4) {
pclka = 1;
break;
}
}
if (k == 4) {
for (j = 0; j < 4; j++) {
if ((prepclk_no % pclkc[j]) == 0 &&
(prepclk_no / pclkc[j]) < 32) {
pclka = prepclk_no / pclkc[j];
break;
}
}
} else {
pclka = 1;
}
if (j == 4)
goto continue_cal;
/* pixel clk directly divided by 5 from fvco */
if (div_5) {
pclkd = 1;
} else {
if (k == 4) {
if (pclk_no % pclka)
goto continue_cal;
else
pclkd = pclk_no / pclka;
} else {
if (pclk_no % pclkb[k])
goto continue_cal;
else
pclkd = pclk_no / pclkb[k];
}
}
if (cfg) {
cfg->pixclock = pixelclk;
cfg->tmdsclock = tmdsclock;
cfg->prediv = nr;
cfg->fbdiv = nf;
cfg->tmds_div_a = tmds_a;
cfg->tmds_div_b = tmds_b;
cfg->tmds_div_c = tmds_c;
cfg->pclk_div_a = pclka;
cfg->pclk_div_b = k;
cfg->pclk_div_c = j;
cfg->pclk_div_d = pclkd;
cfg->vco_div_5_en = div_5;
cfg->fracdiv = frac_div;
}
dev_dbg(inno->dev, "%llu, %llu, %u, %u, %u, %u, %u, %u, %u, %u, %u, %u, %llu\n",
pixelclk, tmdsclock, nr, nf, tmds_a, tmds_b, tmds_c, pclka, k, j, pclkd,
div_5, frac_div);
return pixelclk;
}
static int inno_hdmi_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate);
@@ -595,36 +832,25 @@ static unsigned long inno_hdmi_phy_clk_recalc_rate(struct clk_hw *hw,
static long inno_hdmi_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
int i;
const struct pre_pll_config *cfg = pre_pll_cfg_table;
struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
/* Limit pixel clock under 600MHz */
if (rate > 600000000)
return -EINVAL;
for (; cfg->pixclock != ~0UL; cfg++)
if (cfg->pixclock == rate)
break;
/* XXX: Limit pixel clock under 600MHz */
if (cfg->pixclock > 600000000)
return -EINVAL;
if (cfg->pixclock == ~0UL) {
if (!inno_hdmi_phy_pll_cal(inno, NULL, rate, tmdsclock))
return -EINVAL;
/*
* If there is no dts phy cfg table, use default phy cfg table.
* The tmds clock maximum is 594MHz. So there is no need to check
* whether tmds clock is out of range.
*/
if (!inno->phy_cfg)
return cfg->pixclock;
/* Check if tmds clock is out of dts phy config's range. */
for (i = 0; inno->phy_cfg[i].tmdsclock != ~0UL; i++) {
if (inno->phy_cfg[i].tmdsclock >= tmdsclock)
break;
return rate;
}
if (inno->phy_cfg[i].tmdsclock == ~0UL)
return -EINVAL;
return cfg->pixclock;
}
@@ -633,6 +859,7 @@ static int inno_hdmi_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
{
struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
const struct pre_pll_config *cfg = pre_pll_cfg_table;
struct pre_pll_config rc = {0};
u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
dev_dbg(inno->dev, "%s rate %lu tmdsclk %u\n",
@@ -645,13 +872,17 @@ static int inno_hdmi_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
if (cfg->pixclock == rate && cfg->tmdsclock == tmdsclock)
break;
rc = *cfg;
if (cfg->pixclock == ~0UL) {
dev_err(inno->dev, "unsupported rate %lu\n", rate);
return -EINVAL;
if (!inno_hdmi_phy_pll_cal(inno, &rc, rate, tmdsclock)) {
dev_err(inno->dev, "unsupported rate %lu\n", rate);
return -EINVAL;
}
}
if (inno->plat_data->ops->pre_pll_update)
inno->plat_data->ops->pre_pll_update(inno, cfg);
inno->plat_data->ops->pre_pll_update(inno, &rc);
inno->pixclock = rate;
inno->tmdsclock = tmdsclock;

2
drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
View File

@@ -119,7 +119,7 @@ static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv)
ret = regmap_read_poll_timeout(priv->phy_grf,
GRF_PCIE30PHY_STATUS0,
reg, SRAM_INIT_DONE(reg),
0, 500);
0, RK_PCIE_SRAM_INIT_TIMEOUT);
if (ret) {
dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n",
__func__, reg);

659
drivers/power/supply/rk817_battery.c
View File

File diff suppressed because it is too large Load Diff

37
drivers/power/supply/rk817_charger.c
View File

@@ -198,6 +198,7 @@ enum charger_state {
};
enum rk817_charge_fields {
CHRG_BAT_TAB2,
BOOST_EN, OTG_EN, OTG_SLP_EN, CHRG_CLK_SEL,
CHRG_EN, CHRG_VOL_SEL, CHRG_CT_EN, CHRG_CUR_SEL,
USB_VLIM_EN, USB_VLIM_SEL, USB_ILIM_EN, USB_ILIM_SEL,
@@ -211,11 +212,12 @@ enum rk817_charge_fields {
USB_EXS, USB_EFF,
BAT_DIS_ILIM_STS, BAT_SYS_CMP_DLY, BAT_DIS_ILIM_EN,
BAT_DISCHRG_ILIM,
PLUG_IN_STS, SOC_REG0, SOC_REG1, SOC_REG2,
PLUG_IN_STS, SOC_REG0, SOC_REG1, SOC_REG2, RK817B_FLAG,
F_MAX_FIELDS
};
static const struct reg_field rk817_charge_reg_fields[] = {
[CHRG_BAT_TAB2] = REG_FIELD(0x62, 7, 7),
[SOC_REG0] = REG_FIELD(0x9A, 0, 7),
[SOC_REG1] = REG_FIELD(0x9B, 0, 7),
[SOC_REG2] = REG_FIELD(0x9C, 0, 7),
@@ -262,6 +264,7 @@ static const struct reg_field rk817_charge_reg_fields[] = {
[BAT_DISCHRG_ILIM] = REG_FIELD(0xEC, 0, 2),
[PLUG_IN_STS] = REG_FIELD(0xf0, 6, 6),
[CHRG_CLK_SEL] = REG_FIELD(0xF3, 6, 6),
[RK817B_FLAG] = REG_FIELD(0xFF, 0, 0),
};
struct charger_platform_data {
@@ -333,6 +336,7 @@ struct rk817_charger {
u8 plugout_trigger;
int plugin_irq;
int plugout_irq;
bool is_rk817b;
};
static enum power_supply_property rk817_ac_props[] = {
@@ -483,6 +487,13 @@ static int rk817_charge_field_write(struct rk817_charger *charge,
return regmap_field_write(charge->rmap_fields[field_id], val);
}
static int rk817_charge_field_force_write(struct rk817_charger *charge,
enum rk817_charge_fields field_id,
unsigned int val)
{
return regmap_field_force_write(charge->rmap_fields[field_id], val);
}
static int rk817_charge_get_otg_state(struct rk817_charger *charge)
{
return regulator_is_enabled(charge->otg5v_rdev);
@@ -503,13 +514,8 @@ static void rk817_charge_otg_disable(struct rk817_charger *charge)
int ret;
ret = regulator_disable(charge->otg5v_rdev);
if (ret) {
if (ret)
DBG("disable otg5v failed:%d\n", ret);
return;
}
return;
}
static void rk817_charge_otg_enable(struct rk817_charger *charge)
@@ -517,13 +523,8 @@ static void rk817_charge_otg_enable(struct rk817_charger *charge)
int ret;
ret = regulator_enable(charge->otg5v_rdev);
if (ret) {
if (ret)
DBG("enable otg5v failed:%d\n", ret);
return;
}
return;
}
#ifdef CONFIG_PM_SLEEP
@@ -626,9 +627,12 @@ static void rk817_charge_set_chrg_voltage(struct rk817_charger *charge,
dev_err(charge->dev, "the charge voltage is error!\n");
} else {
voltage = (chrg_vol - 4100) / 50;
rk817_charge_field_write(charge,
CHRG_VOL_SEL,
CHRG_VOL_4100MV + voltage);
if (charge->is_rk817b)
rk817_charge_field_force_write(charge, CHRG_BAT_TAB2, 0);
rk817_charge_field_force_write(charge,
CHRG_VOL_SEL,
CHRG_VOL_4100MV + voltage);
}
}
@@ -1295,6 +1299,7 @@ static void rk817_charge_pre_init(struct rk817_charger *charge)
charge->min_input_voltage = charge->pdata->min_input_voltage;
charge->chrg_finish_cur = charge->pdata->chrg_finish_cur;
charge->chrg_term_mode = charge->pdata->chrg_term_mode;
charge->is_rk817b = rk817_charge_field_read(charge, RK817B_FLAG);
rk817_charge_set_input_voltage(charge, charge->min_input_voltage);

2
drivers/pwm/pwm-rockchip.c
View File

@@ -2499,8 +2499,6 @@ static int rockchip_pwm_remove(struct platform_device *pdev)
}
}
pwmchip_remove(&pc->chip);
if (pc->oneshot_en)
clk_disable(pc->pclk);
clk_unprepare(pc->clk_osc);

8
drivers/soc/rockchip/rockchip_thunderboot_mmc.c
View File

@@ -58,13 +58,17 @@ static int rk_tb_mmc_thread(void *p)
if (readl_poll_timeout(regs + SDMMC_STATUS, status,
!(status & (BIT(10) | GENMASK(7, 4))), 100,
500 * USEC_PER_MSEC))
500 * USEC_PER_MSEC)) {
dev_err(dev, "Controller is occupied!\n");
goto out;
}
if (readl_poll_timeout(regs + SDMMC_IDSTS, status,
!(status & GENMASK(16, 13)), 100,
500 * USEC_PER_MSEC))
500 * USEC_PER_MSEC)) {
dev_err(dev, "DMA is still running!\n");
goto out;
}
status = readl_relaxed(regs + SDMMC_RINTSTS);
if (status & SDMMC_INTR_ERROR) {

3
drivers/spi/spi-rockchip-sfc.c
View File

@@ -1214,6 +1214,9 @@ static struct platform_driver rockchip_sfc_driver = {
.name = "rockchip-sfc",
.of_match_table = rockchip_sfc_dt_ids,
.pm = &rockchip_sfc_pm_ops,
#ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
#endif
},
.probe = rockchip_sfc_probe,
.remove = rockchip_sfc_remove,