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arm64: dts: rockchip: rk3588: Add support for multi-core

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RK3588 is an ARM DynamiQ architecture SoC, including 4 Cortex-A55 cores
and 4 Cortex-A76 cores.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: Id52349b39e28bc5a4fd3d0f17a712cd4c0797db8
This commit is contained in:
Kever Yang
2021-08-27 14:58:25 +08:00
committed by Tao Huang
parent bf6c596646
commit 98e3dce8ad
1 changed files with 90 additions and 10 deletions
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100
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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@@ -41,24 +41,104 @@
};
cpus {
#address-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
cpu-map {
cluster0 {
core0 {
cpu = <&cpu_l0>;
};
core1 {
cpu = <&cpu_l1>;
};
core2 {
cpu = <&cpu_l2>;
};
core3 {
cpu = <&cpu_l3>;
};
};
cluster1 {
core0 {
cpu = <&cpu_b0>;
};
core1 {
cpu = <&cpu_b1>;
};
};
cluster2 {
core0 {
cpu = <&cpu_b2>;
};
core1 {
cpu = <&cpu_b3>;
};
};
};
cpu_l0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
reg = <0x0>;
enable-method = "psci";
};
cpu_l1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x100>;
enable-method = "psci";
};
cpu_l2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x200>;
enable-method = "psci";
};
cpu_l3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x300>;
enable-method = "psci";
};
cpu_b0: cpu@400 {
device_type = "cpu";
compatible = "arm,cortex-a76";
reg = <0x400>;
enable-method = "psci";
};
cpu_b1: cpu@500 {
device_type = "cpu";
compatible = "arm,cortex-a76";
reg = <0x500>;
enable-method = "psci";
};
cpu_b2: cpu@600 {
device_type = "cpu";
compatible = "arm,cortex-a76";
reg = <0x600>;
enable-method = "psci";
};
cpu_b3: cpu@700 {
device_type = "cpu";
compatible = "arm,cortex-a76";
reg = <0x700>;
enable-method = "psci";
};
};
arm-pmu {
compatible = "arm,cortex-a55-pmu", "arm,armv8-pmuv3";
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>;
arm_pmu: arm-pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_LOW>;
interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>,
<&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>;
};
firmware {