ARM: tegra: Enable PL310 dynamic clock gating

The cache controller will stop its clock when idle after several
clock cycles.

Change-Id: Ifc9997d4e7fd4f1e3c6129bac2fd42f8995a069e
Signed-off-by: Todd Poynor <toddpoynor@google.com>

arch/arm/mach-tegra/common.c

@@ -89,6 +89,7 @@ void __init tegra_init_cache(void)
 	writel(0x331, p + L2X0_TAG_LATENCY_CTRL);
 	writel(0x441, p + L2X0_DATA_LATENCY_CTRL);
 	writel(7, p + L2X0_PREFETCH_OFFSET);
+	writel(2, p + L2X0_PWR_CTRL);
 
 	l2x0_init(p, 0x7C480001, 0x8200c3fe);
 #endif