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ARM64: dts: rk3328: add vepu & h265e dts node

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Change-Id: I2990ac7e43d4b2d2efbf5e9cf3abe124e8767648
Signed-off-by: Jung Zhao <jung.zhao@rock-chips.com>
This commit is contained in:
Jung Zhao
2017-04-17 16:38:39 +08:00
committed by Tao Huang
parent 2421ee1a93
commit 998234d929
1 changed files with 62 additions and 22 deletions
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84
arch/arm64/boot/dts/rockchip/rk3328.dtsi
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@@ -558,28 +558,6 @@
resets = <&cru SRST_GPU_A>;
};
h265e_mmu: iommu@ff330200 {
compatible = "rockchip,iommu";
reg = <0x0 0xff330200 0 0x100>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "h265e_mmu";
clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};
vepu_mmu: iommu@ff340800 {
compatible = "rockchip,iommu";
reg = <0x0 0xff340800 0x0 0x40>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vepu_mmu";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};
vpu_mmu: iommu@ff350800 {
compatible = "rockchip,iommu";
reg = <0x0 0xff350800 0x0 0x40>;
@@ -602,6 +580,68 @@
status = "disabled";
};
h265e: h265e@ff330000 {
compatible = "rockchip,h265e";
rockchip,grf = <&grf>;
iommu_enabled = <1>;
iommus = <&h265e_mmu>;
reg = <0x0 0xff330000 0 0x200>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_H265>, <&cru PCLK_H265>,
<&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
<&cru ACLK_RKVENC>, <&cru ACLK_AXISRAM>;
clock-names = "aclk_h265", "pclk_h265", "clk_core",
"clk_dsp", "aclk_venc", "aclk_axi2sram";
rockchip,srv = <&venc_srv>;
mode_bit = <11>;
mode_ctrl = <0x40c>;
name = "h265e";
allocator = <1>;
status = "disabled";
};
h265e_mmu: iommu@ff330200 {
compatible = "rockchip,iommu";
reg = <0x0 0xff330200 0 0x100>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "h265e_mmu";
#iommu-cells = <0>;
};
vepu: vepu@ff340000 {
compatible = "rockchip,rk3328-vepu", "rockchip,vepu";
rockchip,grf = <&grf>;
iommu_enabled = <1>;
iommus = <&vepu_mmu>;
reg = <0x0 0xff340000 0x0 0x400>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk_vcodec", "hclk_vcodec";
resets = <&cru SRST_RKVENC_H264_H>,
<&cru SRST_RKVENC_H264_A>;
reset-names = "video_h", "video_a";
rockchip,srv = <&venc_srv>;
mode_bit = <11>;
mode_ctrl = <0x40c>;
name = "vepu";
allocator = <1>;
status = "disabled";
};
vepu_mmu: iommu@ff340800 {
compatible = "rockchip,iommu";
reg = <0x0 0xff340800 0x0 0x40>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vepu_mmu";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk", "hclk";
#iommu-cells = <0>;
};
venc_srv: venc_srv {
compatible = "rockchip,mpp_service";
};
vop: vop@ff370000 {
compatible = "rockchip,rk3328-vop";
reg = <0x0 0xff370000 0x0 0x3efc>;