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drm/rockchip: vop2: update default axi id for rk3576

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win axi id register is 5 bits, but lut/dci axi id is 4 bits, so lut axi id
should be less then 0xf;

  Cluster0 win0: 0x10, 0x11	[AXI0]
  Cluster0 win1: 0x12, 0x13	[AXI0]
  Cluster1 win0: 6, 7        	[AXI0]
  Cluster1 win1: 8, 9        	[AXI0]
  Esmart0:	 a, b           [AXI0]
  Esmart1:	 c, d           [AXI0]
  Esmart2:	 a, b           [AXI1]
  Esmart3:	 c, d           [AXI1]
  Lut dma rid:	 0x1, 0x2, 0x3  [AXI0]
  DCI dma rid:	 0x4        	[AXI0]
  Metadata rid:	 0x5        	[AXI0]

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: If1148aba4ab5242470511b356ee53db9cccef1eb
This commit is contained in:
Sandy Huang
2024-02-19 16:36:29 +08:00
committed by Tao Huang
parent 3832b4ab01
commit 999eaf4dae
3 changed files with 21 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View File

@@ -729,8 +729,8 @@ struct vop2_cluster_regs {
struct vop_reg dci_en;
struct vop_reg uv_adjust_en;
struct vop_reg csc_range;
struct vop_reg dma_rid;
struct vop_reg dma_rlen;
struct vop_reg dci_dma_rid;
struct vop_reg dci_dma_rlen;
struct vop_reg dci_dma_mst;
struct vop_reg debug_point_h;
struct vop_reg debug_point_v;
@@ -1270,6 +1270,7 @@ struct vop2_ctrl {
struct vop_reg rkmmu_v2_sel_axi;
struct vop_reg dsp_vs_t_sel;
struct vop_reg lut_dma_en;
struct vop_reg lut_use_axi1;
struct vop_reg axi_outstanding_max_num;
struct vop_reg axi_max_outstanding_en;
struct vop_reg hdmi_dclk_out_en;

7
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -3818,7 +3818,7 @@ static int vop2_crtc_atomic_cubic_lut_set(struct drm_crtc *crtc,
*cubic_lut_kvaddr = 0;
}
VOP_MODULE_SET(vop2, vp, lut_dma_rid, vp->lut_dma_rid);
VOP_MODULE_SET(vop2, vp, lut_dma_rid, vp->lut_dma_rid - vp->id);
VOP_MODULE_SET(vop2, vp, cubic_lut_mst, cubic_lut_mst);
VOP_MODULE_SET(vop2, vp, cubic_lut_update_en, 1);
VOP_MODULE_SET(vop2, vp, cubic_lut_en, 1);
@@ -4100,6 +4100,7 @@ static void vop2_initial(struct drm_crtc *crtc)
if (vop2->version == VOP_VERSION_RK3576 && vop2->merge_irq == true)
VOP_CTRL_SET(vop2, vp_intr_merge_en, 1);
VOP_CTRL_SET(vop2, lut_use_axi1, 0);
}
VOP_CTRL_SET(vop2, cfg_done_en, 1);
@@ -5469,8 +5470,8 @@ static void vop3_dci_config(struct vop2_win *win, struct vop2_plane_state *vpsta
VOP_CLUSTER_SET(vop2, win, dci_dma_mst, dci_lut_mst);
/* dci dma rid */
VOP_CLUSTER_SET(vop2, win, dma_rid, win_data->dci_rid_id);
VOP_CLUSTER_SET(vop2, win, dma_rlen, 0);
VOP_CLUSTER_SET(vop2, win, dci_dma_rid, win_data->dci_rid_id);
VOP_CLUSTER_SET(vop2, win, dci_dma_rlen, 0);
VOP_CLUSTER_SET(vop2, win, blk_size_h, blk_size_h);
VOP_CLUSTER_SET(vop2, win, blk_size_v, blk_size_v);

27
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
View File

@@ -1490,7 +1490,7 @@ static const struct vop2_video_port_regs rk3576_vop_vp0_regs = {
.vact_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
.vs_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
.vpost_st_end_f1 = VOP_REG(RK3568_VP0_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
.lut_dma_rid = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0x1f, 4),
.lut_dma_rid = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0xf, 4),
.layer_sel = VOP_REG(RK3528_OVL_PORT0_LAYER_SEL, 0xffff, 0),
.hdr_src_color_ctrl = VOP_REG(RK3528_HDR_SRC_COLOR_CTRL, 0xffffffff, 0),
.hdr_dst_color_ctrl = VOP_REG(RK3528_HDR_DST_COLOR_CTRL, 0xffffffff, 0),
@@ -1590,7 +1590,7 @@ static const struct vop2_video_port_regs rk3576_vop_vp1_regs = {
.vact_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
.vs_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
.vpost_st_end_f1 = VOP_REG(RK3568_VP1_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
.lut_dma_rid = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0x1f, 4),
.lut_dma_rid = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0xf, 4),
.layer_sel = VOP_REG(RK3528_OVL_PORT1_LAYER_SEL, 0xffff, 0),
.color_bar_mode = VOP_REG(RK3568_VP1_COLOR_BAR_CTRL, 0x1, 1),
.color_bar_en = VOP_REG(RK3568_VP1_COLOR_BAR_CTRL, 0x1, 0),
@@ -1662,7 +1662,7 @@ static const struct vop2_video_port_regs rk3576_vop_vp2_regs = {
.vact_st_end_f1 = VOP_REG(RK3568_VP2_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
.vs_st_end_f1 = VOP_REG(RK3568_VP2_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
.vpost_st_end_f1 = VOP_REG(RK3568_VP2_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
.lut_dma_rid = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0x1f, 4),
.lut_dma_rid = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0xf, 4),
.layer_sel = VOP_REG(RK3576_OVL_PORT2_LAYER_SEL, 0xffff, 0),
.color_bar_mode = VOP_REG(RK3568_VP2_COLOR_BAR_CTRL, 0x1, 1),
.color_bar_en = VOP_REG(RK3568_VP2_COLOR_BAR_CTRL, 0x1, 0),
@@ -1701,7 +1701,7 @@ static const struct vop2_video_port_data rk3576_vop_video_ports[] = {
{
.id = 0,
.soc_id = { 0x3576, 0x3576 },
.lut_dma_rid = 0x10,
.lut_dma_rid = 0x1,/* lut axi id length is 4 bits */
.feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN | VOP_FEATURE_VIVID_HDR |
VOP_FEATURE_POST_ACM | VOP_FEATURE_POST_CSC | VOP_FEATURE_OUTPUT_10BIT |
VOP_FEATURE_POST_FRC_V2 | VOP_FEATURE_POST_SHARP,
@@ -1721,7 +1721,7 @@ static const struct vop2_video_port_data rk3576_vop_video_ports[] = {
{
.id = 1,
.soc_id = { 0x3576, 0x3576 },
.lut_dma_rid = 0x11,
.lut_dma_rid = 0x2,/* lut axi id length is 4 bits */
.feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN | VOP_FEATURE_OUTPUT_10BIT |
VOP_FEATURE_POST_FRC_V2,
.gamma_lut_len = 1024,
@@ -1739,7 +1739,7 @@ static const struct vop2_video_port_data rk3576_vop_video_ports[] = {
{
.id = 2,
.soc_id = { 0x3576, 0x3576 },
.lut_dma_rid = 0x12,
.lut_dma_rid = 0x3,/* lut axi id length is 4 bits */
.feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
.gamma_lut_len = 1024,
.max_output = { 1920, 1920 },
@@ -2392,8 +2392,8 @@ static const struct vop2_cluster_regs rk3576_vop_cluster0 = {
.dci_en = VOP_REG(RK3576_CLUSTER0_DCI_CTRL, 1, 0),
.uv_adjust_en = VOP_REG(RK3576_CLUSTER0_DCI_CTRL, 1, 1),
.csc_range = VOP_REG(RK3576_CLUSTER0_DCI_CTRL, 1, 2),
.dma_rid = VOP_REG(RK3576_CLUSTER0_DCI_CTRL, 0x1f, 4),
.dma_rlen = VOP_REG(RK3576_CLUSTER0_DCI_CTRL, 0x3, 12),
.dci_dma_rid = VOP_REG(RK3576_CLUSTER0_DCI_CTRL, 0xf, 4),
.dci_dma_rlen = VOP_REG(RK3576_CLUSTER0_DCI_CTRL, 0x3, 12),
.dci_dma_mst = VOP_REG(RK3576_CLUSTER0_DCI_LUT_MST, 0xffffffff, 0),
.debug_point_h = VOP_REG(RK3576_CLUSTER0_DCI_DBG_CTRL, 0x1fff, 0),
.debug_point_v = VOP_REG(RK3576_CLUSTER0_DCI_DBG_CTRL, 0x1fff, 16),
@@ -3682,9 +3682,9 @@ static const struct vop2_win_data rk3576_vop_win_data[] = {
.vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG,/* gt or avg */
.regs = &rk3576_cluster0_win_data,
.pd_id = VOP2_PD_CLUSTER,
.axi_yrgb_id = 0x02,
.axi_uv_id = 0x03,
.dci_rid_id = 0x13,
.axi_yrgb_id = 0x10,
.axi_uv_id = 0x11,
.dci_rid_id = 0x4,/* dci axi id length is 4 bits */
.possible_crtcs = 0x3,/* vp0 or vp1 */
.max_upscale_factor = 8,
.max_downscale_factor = 8,
@@ -3709,8 +3709,8 @@ static const struct vop2_win_data rk3576_vop_win_data[] = {
.hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG,/* gt or avg */
.vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG,/* gt or avg */
.regs = &rk3576_cluster0_win_data,
.axi_yrgb_id = 0x04,
.axi_uv_id = 0x05,
.axi_yrgb_id = 0x12,
.axi_uv_id = 0x13,
.possible_crtcs = 0x3,/* vp0 or vp1 */
.max_upscale_factor = 8,
.max_downscale_factor = 8,
@@ -4499,6 +4499,7 @@ static const struct vop2_ctrl rk3576_vop_ctrl = {
.aclk_pre_auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 7),
.version = VOP_REG(RK3568_VERSION_INFO, 0xffff, 16),
.lut_dma_en = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0x1, 0),
.lut_use_axi1 = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0x1, 9),
.dsp_vs_t_sel = VOP_REG(RK3576_SYS_PORT_CTRL_IMD, 0x1, 4),
.rkmmu_v2_en = VOP_REG_MASK(RK3576_SYS_MMU_CTRL_IMD, 0x1, 0),
.rkmmu_v2_sel_axi = VOP_REG_MASK(RK3576_SYS_MMU_CTRL_IMD, 0x1, 1),