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arm64: dts: rockchip: add rk3568-evb2-lp4x-v10 for rk3568 evb2
Change-Id: Ic8b384e260abf71b4e9f1f030f46105554558892 Signed-off-by: Wu Liangqing <wlq@rock-chips.com>
This commit is contained in:
Wu Liangqing
@@ -82,6 +82,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-k108.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-rkg11.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-linux.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb2-lp4x-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-linux.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-rk628-bt1120-to-hdmi.dtb
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8
arch/arm64/boot/dts/rockchip/rk3568-evb2-lp4x-v10.dts
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8
arch/arm64/boot/dts/rockchip/rk3568-evb2-lp4x-v10.dts
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@@ -0,0 +1,8 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
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*
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*/
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#include "rk3568-evb2-lp4x-v10.dtsi"
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#include "rk3568-android.dtsi"
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362
arch/arm64/boot/dts/rockchip/rk3568-evb2-lp4x-v10.dtsi
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362
arch/arm64/boot/dts/rockchip/rk3568-evb2-lp4x-v10.dtsi
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@@ -0,0 +1,362 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
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*
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include "rk3568.dtsi"
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#include "rk3568-evb.dtsi"
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/ {
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model = "Rockchip RK3568 EVB1 DDR4 V10 Board";
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compatible = "rockchip,rk3568-ev1-ddr4-v10", "rockchip,rk3568";
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rk_headset: rk-headset {
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compatible = "rockchip_headset";
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headset_gpio = <&gpio4 RK_PC1 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&hp_det>;
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};
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vcc2v5_sys: vcc2v5-ddr {
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compatible = "regulator-fixed";
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regulator-name = "vcc2v5-sys";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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vin-supply = <&vcc3v3_sys>;
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};
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pcie30_avdd0v9: pcie30-avdd0v9 {
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compatible = "regulator-fixed";
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regulator-name = "pcie30_avdd0v9";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <900000>;
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vin-supply = <&vcc3v3_sys>;
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};
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pcie30_avdd1v8: pcie30-avdd1v8 {
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compatible = "regulator-fixed";
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regulator-name = "pcie30_avdd1v8";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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vin-supply = <&vcc3v3_sys>;
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};
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pcie30_3v3: gpio-regulator {
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compatible = "regulator-gpio";
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regulator-name = "pcie30_3v3";
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regulator-min-microvolt = <0100000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
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gpios-states = <0x1>;
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states = <0100000 0x0
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3300000 0x1>;
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};
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vcc3v3_bu: vcc3v3-bu {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_bu";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&vcc5v0_sys>;
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};
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};
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&combphy0_us {
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status = "okay";
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};
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&combphy1_usq {
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status = "okay";
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};
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&combphy2_psq {
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status = "okay";
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};
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/*
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* mipi_dphy0 needs to be enabled
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* when dsi0 is enabled
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*/
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&dsi0 {
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status = "okay";
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};
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&dsi0_in_vp0 {
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status = "okay";
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};
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&dsi0_in_vp1 {
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status = "disabled";
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};
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&dsi0_panel {
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power-supply = <&vcc3v3_lcd0_n>;
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};
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/*
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* mipi_dphy1 needs to be enabled
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* when dsi1 is enabled
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*/
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&dsi1 {
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status = "disabled";
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};
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&dsi1_in_vp0 {
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status = "disabled";
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};
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&dsi1_in_vp1 {
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status = "disabled";
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};
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&dsi1_panel {
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power-supply = <&vcc3v3_lcd1_n>;
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};
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&gmac0 {
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phy-mode = "rgmii";
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clock_in_out = "output";
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snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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/* Reset time is 20ms, 100ms for rtl8211f */
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snps,reset-delays-us = <0 20000 100000>;
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assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
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assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
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assigned-clock-rates = <0>, <125000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&gmac0_miim
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&gmac0_tx_bus2
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&gmac0_rx_bus2
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&gmac0_rgmii_clk
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&gmac0_rgmii_bus>;
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tx_delay = <0x3c>;
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rx_delay = <0x2f>;
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phy-handle = <&rgmii_phy0>;
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status = "disabled";
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};
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&gmac1 {
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phy-mode = "rgmii";
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clock_in_out = "output";
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snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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/* Reset time is 20ms, 100ms for rtl8211f */
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snps,reset-delays-us = <0 20000 100000>;
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assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
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assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
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assigned-clock-rates = <0>, <125000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&gmac1m1_miim
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&gmac1m1_tx_bus2
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&gmac1m1_rx_bus2
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&gmac1m1_rgmii_clk
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&gmac1m1_rgmii_bus>;
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tx_delay = <0x4f>;
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rx_delay = <0x26>;
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phy-handle = <&rgmii_phy1>;
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status = "disabled";
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};
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/*
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* power-supply should switche to vcc3v3_lcd1_n
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* when mipi panel is connected to dsi1.
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*/
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>1x {
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power-supply = <&vcc3v3_lcd0_n>;
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};
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&i2c4 {
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status = "okay";
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gs_mxc6655xa: gs_mxc6655xa@15 {
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status = "okay";
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compatible = "gs_mxc6655xa";
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pinctrl-names = "default";
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pinctrl-0 = <&mxc6655xa_irq_gpio>;
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reg = <0x15>;
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irq-gpio = <&gpio3 RK_PD7 IRQ_TYPE_LEVEL_LOW>;
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irq_enable = <0>;
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poll_delay_ms = <30>;
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type = <SENSOR_TYPE_ACCEL>;
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power-off-in-suspend = <1>;
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layout = <1>;
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};
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};
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&i2c5 {
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status = "disabled";
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};
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&mdio0 {
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rgmii_phy0: phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0x0>;
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};
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};
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&mdio1 {
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rgmii_phy1: phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0x0>;
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};
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};
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&mipi_dphy0 {
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status = "okay";
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};
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&mipi_dphy1 {
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status = "disabled";
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};
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&pcie2x1 {
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reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
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vpcie3v3-supply = <&pcie30_3v3>;
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status = "status";
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};
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&pcie30phy {
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status = "status";
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};
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&pcie3x2 {
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reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
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vpcie3v3-supply = <&pcie30_3v3>;
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status = "status";
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};
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&pinctrl {
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headphone {
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hp_det: hp-det {
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rockchip,pins = <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
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};
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};
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mxc6655xa {
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mxc6655xa_irq_gpio: mxc6655xa_irq_gpio {
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rockchip,pins = <RK_GPIO3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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sdio-pwrseq {
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wifi_enable_h: wifi-enable-h {
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rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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wifi_32k: wifi-32k {
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rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
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};
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};
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wireless-wlan {
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wifi_host_wake_irq: wifi-host-wake-irq {
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rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
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};
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};
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wireless-bluetooth {
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uart1_gpios: uart1-gpios {
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rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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&sdio_pwrseq {
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compatible = "mmc-pwrseq-simple";
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clocks = <&pmucru CLK_RTC_32K>;
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clock-names = "ext_clock";
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pinctrl-names = "default";
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pinctrl-0 = <&wifi_enable_h &wifi_32k>;
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/*
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* On the module itself this is one of these (depending
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* on the actual card populated):
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* - SDIO_RESET_L_WL_REG_ON
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* - PDN (power down when low)
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*/
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reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
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};
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&sdmmc1 {
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max-frequency = <150000000>;
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supports-sdio;
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bus-width = <4>;
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disable-wp;
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cap-sd-highspeed;
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cap-sdio-irq;
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keep-power-in-suspend;
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mmc-pwrseq = <&sdio_pwrseq>;
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non-removable;
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
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sd-uhs-sdr104;
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status = "okay";
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};
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&sdmmc2 {
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status = "disabled";
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};
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&uart1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
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};
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&vcc3v3_lcd0_n {
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gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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&vcc3v3_lcd1_n {
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gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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&wireless_wlan {
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compatible = "wlan-platdata";
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rockchip,grf = <&grf>;
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pinctrl-names = "default";
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pinctrl-0 = <&wifi_host_wake_irq>;
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wifi_chip_type = "ap6398s";
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WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&wireless_bluetooth {
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compatible = "bluetooth-platdata";
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clocks = <&pmucru CLK_RTC_32K>;
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clock-names = "ext_clock";
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//wifi-bt-power-toggle;
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uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default", "rts_gpio";
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pinctrl-0 = <&uart1m0_rtsn>;
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pinctrl-1 = <&uart1_gpios>;
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BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
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BT,wake_gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
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BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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