arm64: meson: odroid-go-ultra: add DSI panel

This commit is contained in:
adamg
2024-01-23 23:41:40 +00:00
parent 3701872da3
commit 9a8cb27414

View File

@@ -196,6 +196,14 @@
reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
};
panel_backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm_ef 1 40000 0>;
brightness-levels = <0 255>;
num-interpolated-steps = <255>;
default-brightness-level = <255>;
};
leds {
compatible = "gpio-leds";
@@ -576,6 +584,8 @@
};
vcc_lcd: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_lcd";
@@ -634,6 +644,12 @@
};
};
&pwm_ef {
status = "okay";
pinctrl-0 = <&pwm_f_h_pins>;
pinctrl-names = "default";
};
&saradc {
status = "okay";
vref-supply = <&vddio_ao1v8>;
@@ -720,3 +736,53 @@
status = "okay";
phy-supply = <&usb_host>;
};
&mipi_dsi {
status = "okay";
assigned-clocks = <&clkc CLKID_GP0_PLL>,
<&clkc CLKID_MIPI_DSI_PXCLK_SEL>,
<&clkc CLKID_MIPI_DSI_PXCLK>,
<&clkc CLKID_CTS_ENCL_SEL>,
<&clkc CLKID_VCLK2_SEL>;
assigned-clock-parents = <0>,
<&clkc CLKID_GP0_PLL>,
<0>,
<&clkc CLKID_VCLK2_DIV1>,
<&clkc CLKID_GP0_PLL>;
assigned-clock-rates = <344976000>,
<0>,
<344976000>,
<0>,
<0>;
panel@0 {
compatible = "odroid,go-ultra-panel", "sitronix,st7701";
reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH>;
IOVCC-supply = <&vcc_lcd>;
VCC-supply = <&vcc_lcd>;
backlight = <&panel_backlight>;
rotation = <270>;
reg = <0>;
port {
mipi_in_panel: endpoint {
remote-endpoint = <&mipi_out_panel>;
};
};
};
};
&mipi_analog_dphy {
status = "okay";
};
&mipi_dphy {
status = "okay";
};
&mipi_dsi_panel_port {
mipi_out_panel: endpoint {
remote-endpoint = <&mipi_in_panel>;
};
};