shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-06 19:08:57 +09:00
Code Issues Packages Projects Releases Wiki Activity

phy: rockchip-usb: disable commononn for ehci-phy on rk3288

Browse Source 
We found that the system was blocked in EHCI when perform suspend or
reboot on RK3288 platform, the root cause is that EHCI (auto) suspend
causes the corresponding usb-phy into suspend mode which would power
down the inner PLL blocks in usb-phy if the COMMONONN is set to 1'b1.

The PLL output clocks contained CLK480M, CLK12MOHCI, CLK48MOHCI, PHYCLOCK0
and so on, these clocks are not only supplied for EHCI and OHCI, but also
supplied for GPU and other external modules, so setting COMMONONN to 1'b0
to keep the inner PLL blocks in usb-phy always powered.

Change-Id: Ifb7f3d233cf72155aa54d20b15a62b683944a526
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This commit is contained in:
Frank Wang
2017-12-26 10:43:03 +08:00
committed by Tao Huang
parent 676cc8f42b
commit 9a99be4ef2
1 changed files with 17 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
drivers/phy/rockchip/phy-rockchip-usb.c
View File

@@ -202,10 +202,11 @@ static void rockchip_usb_phy_action(void *data)
static int rockchip_usb_phy_init(struct rockchip_usb_phy_base *base,
struct device_node *child)
{
struct device_node *np = base->dev->of_node;
struct rockchip_usb_phy *rk_phy;
unsigned int reg_offset;
const char *clk_name;
struct clk_init_data init;
struct clk_init_data init = {};
int err, i;
rk_phy = devm_kzalloc(base->dev, sizeof(*rk_phy), GFP_KERNEL);
@@ -295,6 +296,21 @@ static int rockchip_usb_phy_init(struct rockchip_usb_phy_base *base,
rk_phy->vbus = NULL;
}
/*
* Setting the COMMONONN to 1'b0 for EHCI PHY on RK3288 SoC.
*
* EHCI (auto) suspend causes the corresponding usb-phy into suspend
* mode which would power down the inner PLL blocks in usb-phy if the
* COMMONONN is set to 1'b1. The PLL output clocks contained CLK480M,
* CLK12MOHCI, CLK48MOHCI, PHYCLOCK0 and so on, these clocks are not
* only supplied for EHCI and OHCI, but also supplied for GPU and other
* external modules, so setting COMMONONN to 1'b0 to keep the inner PLL
* blocks in usb-phy always powered.
*/
if (of_device_is_compatible(np, "rockchip,rk3288-usb-phy") &&
reg_offset == 0x334)
regmap_write(base->reg_base, reg_offset, BIT(16));
/*
* When acting as uart-pipe, just keep clock on otherwise
* only power up usb phy when it use, so disable it when init