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arm64: dts: rockchip: rk3588: remove hdmiphy pll config

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Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Ib72a7a0384f564699926af4b60d978021e995eb8
This commit is contained in:
Zhang Yubing
2022-05-05 11:21:10 +08:00
committed by Tao Huang
parent 436e63d852
commit 9afbb1484f
2 changed files with 2 additions and 31 deletions
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27
arch/arm64/boot/dts/rockchip/rk3588.dtsi
View File

@@ -905,33 +905,6 @@
};
};
&vop {
clocks = <&cru ACLK_VOP>,
<&cru HCLK_VOP>,
<&cru DCLK_VOP0>,
<&cru DCLK_VOP1>,
<&cru DCLK_VOP2>,
<&cru DCLK_VOP3>,
<&cru PCLK_VOP_ROOT>,
<&cru DCLK_VOP0_SRC>,
<&cru DCLK_VOP1_SRC>,
<&cru DCLK_VOP2_SRC>,
<&hdptxphy_hdmi0>,
<&hdptxphy_hdmi1>;
clock-names = "aclk_vop",
"hclk_vop",
"dclk_vp0",
"dclk_vp1",
"dclk_vp2",
"dclk_vp3",
"pclk_vop",
"dclk_src_vp0",
"dclk_src_vp1",
"dclk_src_vp2",
"hdmi0_phy_pll",
"hdmi1_phy_pll";
};
&vp0 {
vp0_out_dp1: endpoint@3 {
reg = <3>;

6
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
View File

@@ -3648,8 +3648,7 @@
<&cru PCLK_VOP_ROOT>,
<&cru DCLK_VOP0_SRC>,
<&cru DCLK_VOP1_SRC>,
<&cru DCLK_VOP2_SRC>,
<&hdptxphy_hdmi0>;
<&cru DCLK_VOP2_SRC>;
clock-names = "aclk_vop",
"hclk_vop",
"dclk_vp0",
@@ -3659,8 +3658,7 @@
"pclk_vop",
"dclk_src_vp0",
"dclk_src_vp1",
"dclk_src_vp2",
"hdmi0_phy_pll";
"dclk_src_vp2";
resets = <&cru SRST_A_VOP>,
<&cru SRST_H_VOP>,
<&cru SRST_D_VOP0>,