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misc: rk628: gvi: enable 8 pixel align for gvi compatibility

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Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I86422a7bfe5fc2165cd04003665c6b76af21338b
This commit is contained in:
Sandy Huang
2023-11-01 10:12:50 +08:00
committed by Tao Huang
parent 7199ce284d
commit 9b99adc51a
2 changed files with 3 additions and 0 deletions
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1
drivers/misc/rk628/rk628.h
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@@ -65,6 +65,7 @@
#define GRF_AS_DSIPHY_MASK BIT(0)
#define GRF_AS_DSIPHY(x) UPDATE(x, 0, 0)
#define GRF_SCALER_CON0 0x0010
#define SCL_8_PIXEL_ALIGN(x) HIWORD_UPDATE(x, 12, 12)
#define SCL_VER_DOWN_MODE(x) HIWORD_UPDATE(x, 8, 8)
#define SCL_HOR_DOWN_MODE(x) HIWORD_UPDATE(x, 7, 7)
#define SCL_BIC_COE_SEL(x) HIWORD_UPDATE(x, 6, 5)

2
drivers/misc/rk628/rk628_gvi.c
View File

@@ -120,6 +120,8 @@ static void rk628_gvi_pre_enable(struct rk628 *rk628, struct rk628_gvi *gvi)
rk628_i2c_update_bits(rk628, GVI_SYS_RST, SYS_RST_SOFT_RST, 0);
udelay(10);
rk628_i2c_write(rk628, GRF_SCALER_CON0, SCL_8_PIXEL_ALIGN(1));
rk628_i2c_update_bits(rk628, GVI_SYS_CTRL0, SYS_CTRL0_LANE_NUM_MASK,
SYS_CTRL0_LANE_NUM(gvi->lanes - 1));
rk628_i2c_update_bits(rk628, GVI_SYS_CTRL0, SYS_CTRL0_BYTE_MODE_MASK,