shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-07 19:30:30 +09:00
Code Issues Packages Projects Releases Wiki Activity

arm64: dts: rockchip: rk3328: fix vepu clk define error

Browse Source 
1.vepu aclk is ACLK_H264 and hclk is HCLK_H264
2.vepu need clk_core clk define
3.add h264&h265 power domain

Change-Id: I419e544cf86d90b2b8d88dd13dfed49d31a24991
Signed-off-by: Xinhuang Li <buluess.li@rock-chips.com>
This commit is contained in:
Xinhuang Li
2017-12-07 15:36:27 +08:00
committed by Tao Huang
parent 210567cbd8
commit 9c104b0341
1 changed files with 7 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm64/boot/dts/rockchip/rk3328.dtsi
View File

@@ -595,6 +595,7 @@
mode_ctrl = <0x40c>;
name = "h265e";
allocator = <1>;
power-domains = <&power RK3328_PD_HEVC>;
status = "disabled";
};
@@ -614,8 +615,10 @@
iommus = <&vepu_mmu>;
reg = <0x0 0xff340000 0x0 0x400>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk_vcodec", "hclk_vcodec";
clocks = <&cru ACLK_H264>, <&cru HCLK_H264>,
<&cru SCLK_VENC_CORE>;
clock-names = "aclk_vcodec", "hclk_vcodec",
"clk_core";
resets = <&cru SRST_RKVENC_H264_H>,
<&cru SRST_RKVENC_H264_A>;
reset-names = "video_h", "video_a";
@@ -624,6 +627,7 @@
mode_ctrl = <0x40c>;
name = "vepu";
allocator = <1>;
power-domains = <&power RK3328_PD_HEVC>;
status = "disabled";
};
@@ -632,7 +636,7 @@
reg = <0x0 0xff340800 0x0 0x40>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vepu_mmu";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clocks = <&cru ACLK_H264>, <&cru HCLK_H264>;
clock-names = "aclk", "hclk";
power-domains = <&power RK3328_PD_HEVC>;
#iommu-cells = <0>;