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arm64: dts: rockchip: rv1126b/bp: update opp-table for cpu/npu/dmc/enc
Change-Id: If9fd7ed8e043de38bdf82da4afc468f5c150d1d7 Signed-off-by: Liang Chen <cl@rock-chips.com>
This commit is contained in:
Liang Chen
@@ -205,6 +205,8 @@
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clock-output-names = "clk_core_pvtpll";
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assigned-clocks = <&pvtpll_core>;
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assigned-clock-rates = <1200000000>;
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nvmem-cells = <&cpu_opp_info>;
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nvmem-cell-names = "opp-info";
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};
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pvtpll_isp: pvtpll-isp@21c60000 {
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@@ -223,7 +225,7 @@
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#clock-cells = <0>;
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clock-output-names = "clk_vepu_pvtpll";
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assigned-clocks = <&pvtpll_enc>;
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assigned-clock-rates = <480000000>;
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assigned-clock-rates = <550000000>;
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};
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pvtpll_aisp: pvtpll-aisp@21fc0000 {
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@@ -245,6 +247,8 @@
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clock-output-names = "clk_npu_pvtpll";
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assigned-clocks = <&pvtpll_npu>;
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assigned-clock-rates = <800000000>;
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nvmem-cells = <&npu_opp_info>;
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nvmem-cell-names = "opp-info";
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};
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};
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@@ -307,8 +311,11 @@
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compatible = "operating-points-v2";
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opp-shared;
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nvmem-cells = <&cpu_leakage>;
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nvmem-cell-names = "leakage";
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mbist-vmin = <850000 900000 950000>;
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nvmem-cells = <&cpu_leakage>, <&cpu_opp_info>, <&cpu_mbist_vmin>, <&cpu_pvtpll>,
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<&specification_serial_number>;
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nvmem-cell-names = "leakage", "opp-info", "mbist-vmin", "pvtm",
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"specification_serial_number";
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rockchip,pvtm-voltage-sel = <
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0 1669 0
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@@ -318,8 +325,8 @@
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1805 1849 4
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1850 1894 5
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1895 1939 6
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1940 1984 7
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1985 2029 8
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1940 2029 7
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2030 9999 8
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>;
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rockchip,pvtm-pvtpll;
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rockchip,pvtm-offset = <0x54>;
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@@ -337,6 +344,8 @@
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opp-594000000 {
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opp-hz = /bits/ 64 <594000000>;
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opp-microvolt = <850000 850000 1100000>;
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opp-microvolt-L0 = <900000 900000 1100000>;
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opp-microvolt-L1 = <875000 875000 1100000>;
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clock-latency-ns = <40000>;
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opp-suspend;
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};
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@@ -499,13 +508,18 @@
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dmc_opp_table: dmc-opp-table {
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compatible = "operating-points-v2";
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mbist-vmin = <850000 900000 950000>;
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nvmem-cells = <&log_leakage>, <&dmc_opp_info>, <&log_mbist_vmin>,
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<&specification_serial_number>;
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nvmem-cell-names = "leakage", "opp-info", "mbist-vmin",
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"specification_serial_number";
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rockchip,temp-hysteresis = <5000>;
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rockchip,low-temp = <10000>;
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rockchip,low-temp-min-volt = <950000>;
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opp-1560000000 {
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opp-hz = /bits/ 64 <1560000000>;
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opp-microvolt = <900000 900000 950000>;
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opp-1332000000 {
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opp-hz = /bits/ 64 <1332000000>;
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opp-microvolt = <862500 862500 950000>;
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};
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};
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@@ -1948,6 +1962,33 @@
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npu_leakage: npu-leakage@34 {
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reg = <0x34 0x1>;
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};
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cpu_pvtpll: cpu-pvtpll@3a {
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reg = <0x3a 0x2>;
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};
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npu_pvtpll: npu-pvtpll@3c {
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reg = <0x3c 0x2>;
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};
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cpu_opp_info: cpu-opp-info@48 {
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reg = <0x48 0x6>;
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};
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dmc_opp_info: dmc-opp-info@4e {
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reg = <0x4e 0x6>;
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};
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npu_opp_info: npu-opp-info@54 {
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reg = <0x54 0x6>;
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};
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cpu_mbist_vmin: cpu-mbist-vmin@74 {
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reg = <0x74 0x1>;
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bits = <0 4>;
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};
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log_mbist_vmin: log-mbist-vmin@74 {
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reg = <0x74 0x1>;
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bits = <4 4>;
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};
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npu_mbist_vmin: npu-mbist-vmin@75 {
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reg = <0x75 0x1>;
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bits = <0 4>;
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};
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};
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tsadc: tsadc@20bb0000 {
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@@ -3182,12 +3223,12 @@
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interrupt-names = "irq_rkvenc";
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clocks = <&cru ACLK_VEPU>, <&cru HCLK_VEPU>, <&cru CLK_CORE_VEPU>;
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clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
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rockchip,normal-rates = <396000000>, <0>, <480000000>;
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rockchip,normal-rates = <396000000>, <0>, <550000000>;
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resets = <&cru SRST_ARESETN_VEPU>, <&cru SRST_HRESETN_VEPU>,
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<&cru SRST_RESETN_CORE_VEPU>;
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reset-names = "video_a", "video_h", "video_core";
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assigned-clocks = <&cru ACLK_VEPU>, <&cru CLK_CORE_VEPU>;
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assigned-clock-rates = <396000000>, <480000000>;
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assigned-clock-rates = <396000000>, <550000000>;
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iommus = <&rkvenc_mmu>;
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rockchip,srv = <&mpp_srv>;
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rockchip,taskqueue-node = <0>;
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@@ -3202,17 +3243,26 @@
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rkvenc_opp_table: rkvenc-opp-table {
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compatible = "operating-points-v2";
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mbist-vmin = <850000 900000 950000>;
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nvmem-cells = <&log_leakage>, <&log_mbist_vmin>, <&specification_serial_number>;
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nvmem-cell-names = "leakage", "mbist-vmin", "specification_serial_number";
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rockchip,temp-hysteresis = <5000>;
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rockchip,low-temp = <10000>;
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rockchip,low-temp-min-volt = <950000>;
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rockchip,leakage-voltage-sel = <
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1 17 0
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18 254 1
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>;
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opp-396000000 {
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opp-hz = /bits/ 64 <396000000>;
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opp-microvolt = <862500 862500 950000>;
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};
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opp-480000000 {
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opp-hz = /bits/ 64 <480000000>;
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opp-microvolt = <900000 900000 950000>;
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};
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opp-550000000 {
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opp-hz = /bits/ 64 <550000000>;
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opp-microvolt = <950000 950000 950000>;
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opp-microvolt = <900000 900000 950000>;
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opp-microvolt-L0 = <925000 925000 950000>;
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};
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};
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@@ -3339,8 +3389,11 @@
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npu_opp_table: npu-opp-table {
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compatible = "operating-points-v2";
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nvmem-cells = <&npu_leakage>, <&specification_serial_number>;
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nvmem-cell-names = "leakage", "specification_serial_number";
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mbist-vmin = <850000 900000 950000>;
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nvmem-cells = <&npu_leakage>, <&npu_opp_info>, <&npu_mbist_vmin>, <&npu_pvtpll>,
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<&specification_serial_number>;
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nvmem-cell-names = "leakage", "opp-info", "mbist-vmin", "pvtm",
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"specification_serial_number";
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rockchip,init-freq = <800000>;
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rockchip,supported-hw;
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@@ -3353,7 +3406,7 @@
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1130 1169 5
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1170 1209 6
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1210 1249 7
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1250 1299 8
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1250 9999 8
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>;
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rockchip,pvtm-pvtpll;
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rockchip,pvtm-offset = <0x54>;
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@@ -3399,18 +3452,20 @@
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opp-800000000 {
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opp-supported-hw = <0xff 0xffff>;
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opp-hz = /bits/ 64 <800000000>;
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opp-microvolt = <925000 925000 1050000>;
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opp-microvolt = <900000 900000 1050000>;
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};
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opp-900000000 {
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opp-supported-hw = <0xff 0xffff>;
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opp-hz = /bits/ 64 <900000000>;
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opp-microvolt = <975000 975000 1050000>;
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opp-microvolt = <950000 950000 1050000>;
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opp-microvolt-L0 = <975000 975000 1050000>;
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};
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opp-950000000 {
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opp-supported-hw = <0xff 0xffff>;
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opp-hz = /bits/ 64 <950000000>;
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opp-microvolt = <975000 975000 1050000>;
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opp-microvolt = <950000 950000 1050000>;
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opp-microvolt-L0 = <1000000 1000000 1050000>;
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opp-microvolt-L1 = <975000 975000 1050000>;
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};
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};
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@@ -8,6 +8,27 @@
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/ {
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};
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&pvtpll_enc {
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assigned-clock-rates = <480000000>;
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};
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&rkvenc {
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rockchip,normal-rates = <396000000>, <0>, <480000000>;
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assigned-clock-rates = <396000000>, <480000000>;
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};
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&rkvenc_opp_table {
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/delete-node/ opp-550000000;
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opp-480000000 {
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opp-hz = /bits/ 64 <480000000>;
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opp-microvolt = <900000 900000 950000>;
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};
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opp-555000000 {
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opp-hz = /bits/ 64 <555000000>;
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opp-microvolt = <950000 950000 950000>;
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};
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};
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&npu_opp_table {
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rockchip,init-freq = <600000>;
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};
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