clk: rockchip: rk3368: add ddrc clock support

Add a ddrc clock into clk branches, so we can do ddr frequency
scaling on rk3368 platform in future.

Change-Id: Ie7fd2e8d8bdf8b9ff843ca13e848f772adaa109a
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

drivers/clk/rockchip/clk-rk3368.c

@@ -340,6 +340,9 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
 			RK3368_CLKGATE_CON(1), 8, GFLAGS),
 	GATE(0, "gpll_ddr", "gpll", 0,
 			RK3368_CLKGATE_CON(1), 9, GFLAGS),
+	COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
+			RK3368_CLKSEL_CON(13), 4, 1, 0, 0, ROCKCHIP_DDRCLK_SCPI),
+
 	COMPOSITE_NOGATE_DIVTBL(0, "ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
 			RK3368_CLKSEL_CON(13), 4, 1, MFLAGS, 0, 2, DFLAGS, div_ddrphy_t),
 

include/dt-bindings/clock/rk3368-cru.h

@@ -91,6 +91,7 @@
 #define SCLK_TIMER13		136
 #define SCLK_TIMER14		137
 #define SCLK_TIMER15		138
+#define SCLK_DDRCLK		139
 
 #define DCLK_VOP		190
 #define MCLK_CRYPTO		191