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ARM: dts: rockchip: rv1106-smd-cam: add rk803 & sc132gs node

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RMSL132 module contains RK803 and SC132GS.

Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: Ifc7d36c76c319645d5f7d8dce2c2ddff018bc306
This commit is contained in:
Lin Jinhan
2022-05-24 17:06:18 +08:00
committed by Tao Huang
parent 0cb5f462d0
commit 9d79315abd
1 changed files with 154 additions and 0 deletions
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154
arch/arm/boot/dts/rv1106-smd-cam.dtsi
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@@ -69,6 +69,83 @@
};
};
&csi2_dphy2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
dphy2_in: endpoint@1 {
reg = <1>;
remote-endpoint = <&sc132gs_out>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
dphy2_out: endpoint@1 {
reg = <1>;
remote-endpoint = <&mipi1_csi2_input>;
};
};
};
};
&i2c3 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c3m2_xfer>;
sc132gs: sc132gs@30 {
compatible = "smartsens,sc132gs";
status = "okay";
reg = <0x30>;
clocks = <&cru MCLK_REF_MIPI1>;
clock-names = "xvclk";
reset-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&mipi_refclk_out1>;
avdd-supply = <&cam_ir_vcc>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
ir-cut = <&cam_ircut0>;
port {
sc132gs_out: endpoint {
remote-endpoint = <&dphy2_in>;
data-lanes = <1 2>;
};
};
};
vcsel_rk803: vcsel_rk803@63 {
compatible = "rockchip,rk803";
status = "okay";
reg = <0x63>;
dvdd-supply = <&cam_ir_vcc>;
gpio-encc1-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; //Flood
gpio-encc2-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; //PRO
};
};
&i2c4 {
status = "okay";
@@ -168,8 +245,73 @@
};
};
&mipi1_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi1_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&dphy2_out>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi1_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi1_in>;
data-lanes = <1 2>;
};
};
};
};
&rkcif_mipi_lvds1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mipi_pins>;
port {
/* MIPI CSI-2 endpoint */
cif_mipi1_in: endpoint {
remote-endpoint = <&mipi1_csi2_output>;
data-lanes = <1 2>;
};
};
};
&rkcif_mipi_lvds1_sditf {
status = "okay";
port {
/* MIPI CSI-2 endpoint */
mipi_lvds1_sditf: endpoint {
remote-endpoint = <&isp1_in>;
data-lanes = <1 2>;
};
};
};
&rkisp {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mipi_pins>;
max-input = <1920 1280 30>;
};
&rkisp_vir0 {
@@ -184,6 +326,18 @@
};
};
&rkisp_vir1 {
status = "okay";
ports {
port@0 {
isp1_in: endpoint {
remote-endpoint = <&mipi_lvds1_sditf>;
};
};
};
};
&pinctrl {
cam {
/* rgb camera power en */