shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-10 12:57:06 +09:00
Code Issues Packages Projects Releases Wiki Activity

mmc: sdhci-of-dwcmshc: Fix DLL settings

Browse Source 
We shouldn't enable any DLL settings in low speed and
always try to reset all of them in case of any leave-out
from previous stage.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Iccd5dde85425d3c5981300da5aba9563b2f8b821
This commit is contained in:
Shawn Lin
2021-03-26 09:34:18 +08:00
committed by Tao Huang
parent 5c7123ea0f
commit 9df33edc9a
1 changed files with 12 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
drivers/mmc/host/sdhci-of-dwcmshc.c
View File

@@ -138,10 +138,6 @@ static void dwcmshc_rk_set_clock(struct sdhci_host *host, unsigned int clock)
host->mmc->actual_clock = 0;
/* DO NOT TOUCH THIS SETTING */
extra = DWCMSHC_EMMC_DLL_DLYENA |
DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
if (clock == 0)
return;
@@ -162,8 +158,10 @@ static void dwcmshc_rk_set_clock(struct sdhci_host *host, unsigned int clock)
sdhci_writel(host, extra, DWCMSHC_HOST_CTRL3);
if (clock <= 400000) {
/* Disable DLL to reset sample clock */
/* Disable DLL and reset both of sample and drive clock */
sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_RXCLK);
sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
return;
}
@@ -172,6 +170,15 @@ static void dwcmshc_rk_set_clock(struct sdhci_host *host, unsigned int clock)
udelay(1);
sdhci_writel(host, 0x0, DWCMSHC_EMMC_DLL_CTRL);
/*
* We shouldn't set DLL_RXCLK_NO_INVERTER for identify mode but
* we must set it in higher speed mode.
*/
extra = DWCMSHC_EMMC_DLL_DLYENA |
DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
/* Init DLL settings */
extra = 0x5 << DWCMSHC_EMMC_DLL_START_POINT |
0x2 << DWCMSHC_EMMC_DLL_INC |