net: wireless: rockchip: rkwifi: bcmdhd: Add rk wifi pcie APIs

Fix the error from dhd pcie interface.

Change-Id: I0f89e7c1a36aa289733082410f6fe65c27481cf8
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This commit is contained in:
Jon Lin
2022-05-07 15:17:19 +08:00
committed by Tao Huang
parent d591c3f6ef
commit 9e093149af
4 changed files with 49 additions and 0 deletions

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@@ -30,6 +30,12 @@ config BCMDHD_PCIE
endchoice
config PCIEASPM_ROCKCHIP_WIFI_EXTENSION
bool "Extend ASPM function"
depends on BCMDHD_PCIE && PCIEASPM_EXT
help
This enables the extensions APIs for ASPM control.
config BCMDHD_FW_PATH
depends on BCMDHD
string "Firmware path"

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@@ -65,6 +65,7 @@
#include <asm/uaccess.h>
#include <asm/unaligned.h>
#include <dhd_linux_priv.h>
#include <rk_dhd_pcie_linux.h>
#include <epivers.h>
#include <bcmutils.h>
@@ -12518,6 +12519,9 @@ dhd_bus_start(dhd_pub_t *dhdp)
dhd_bus_l1ss_enable_rc_ep(dhdp->bus, TRUE);
#endif /* BT_OVER_PCIE */
if (IS_ENABLED(CONFIG_PCIEASPM_ROCKCHIP_WIFI_EXTENSION))
rk_dhd_bus_l1ss_enable_rc_ep(dhdp->bus, TRUE);
#if defined(CONFIG_ARCH_EXYNOS) && defined(BCMPCIE)
#if !defined(CONFIG_SOC_EXYNOS8890) && !defined(SUPPORT_EXYNOS7420)
/* XXX: JIRA SWWLAN-139454: Added L1ss enable

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@@ -47,6 +47,7 @@
#include <pcicfg.h>
#include <dhd_pcie.h>
#include <dhd_linux.h>
#include <rk_dhd_pcie_linux.h>
#ifdef OEM_ANDROID
#ifdef CONFIG_ARCH_MSM
#if defined(CONFIG_PCI_MSM) || defined(CONFIG_ARCH_MSM8996)
@@ -617,6 +618,8 @@ dhd_bus_is_rc_ep_l1ss_capable(dhd_bus_t *bus)
uint32 rc_l1ss_cap;
uint32 ep_l1ss_cap;
if (IS_ENABLED(CONFIG_PCIEASPM_ROCKCHIP_WIFI_EXTENSION))
return rk_dhd_bus_is_rc_ep_l1ss_capable(bus);
/* RC Extendend Capacility */
rc_l1ss_cap = dhdpcie_access_cap(bus->rc_dev, PCIE_EXTCAP_ID_L1SS,
PCIE_EXTCAP_L1SS_CONTROL_OFFSET, TRUE, FALSE, 0);

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@@ -0,0 +1,36 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Rockchip PCIe Apis For WIFI
*
* Copyright (c) 2022, Rockchip Electronics Co., Ltd.
*/
#ifndef __RK_DHD_PCIE_LINUX_H__
#define __RK_DHD_PCIE_LINUX_H__
#include <typedefs.h>
#include <sbchipc.h>
#include <pcie_core.h>
#include <dhd_pcie.h>
#include <linux/aspm_ext.h>
static inline void
rk_dhd_bus_l1ss_enable_rc_ep(dhd_bus_t *bus, bool enable)
{
if (!bus->rc_ep_aspm_cap || !bus->rc_ep_l1ss_cap) {
pr_err("%s: NOT L1SS CAPABLE rc_ep_aspm_cap: %d rc_ep_l1ss_cap: %d\n",
__func__, bus->rc_ep_aspm_cap, bus->rc_ep_l1ss_cap);
return;
}
/* Disable ASPM of RC and EP */
pcie_aspm_ext_l1ss_enable(bus->dev, bus->rc_dev, enable);
}
static inline bool
rk_dhd_bus_is_rc_ep_l1ss_capable(dhd_bus_t *bus)
{
return pcie_aspm_ext_is_rc_ep_l1ss_capable(bus->dev, bus->rc_dev);
}
#endif /* __RK_DHD_PCIE_LINUX_H__ */