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net: wireless: rockchip: rkwifi: bcmdhd: Add rk wifi pcie APIs
Fix the error from dhd pcie interface. Change-Id: I0f89e7c1a36aa289733082410f6fe65c27481cf8 Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
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@@ -30,6 +30,12 @@ config BCMDHD_PCIE
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endchoice
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config PCIEASPM_ROCKCHIP_WIFI_EXTENSION
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bool "Extend ASPM function"
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depends on BCMDHD_PCIE && PCIEASPM_EXT
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help
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This enables the extensions APIs for ASPM control.
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config BCMDHD_FW_PATH
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depends on BCMDHD
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string "Firmware path"
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@@ -65,6 +65,7 @@
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#include <asm/uaccess.h>
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#include <asm/unaligned.h>
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#include <dhd_linux_priv.h>
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#include <rk_dhd_pcie_linux.h>
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#include <epivers.h>
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#include <bcmutils.h>
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@@ -12518,6 +12519,9 @@ dhd_bus_start(dhd_pub_t *dhdp)
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dhd_bus_l1ss_enable_rc_ep(dhdp->bus, TRUE);
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#endif /* BT_OVER_PCIE */
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if (IS_ENABLED(CONFIG_PCIEASPM_ROCKCHIP_WIFI_EXTENSION))
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rk_dhd_bus_l1ss_enable_rc_ep(dhdp->bus, TRUE);
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#if defined(CONFIG_ARCH_EXYNOS) && defined(BCMPCIE)
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#if !defined(CONFIG_SOC_EXYNOS8890) && !defined(SUPPORT_EXYNOS7420)
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/* XXX: JIRA SWWLAN-139454: Added L1ss enable
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@@ -47,6 +47,7 @@
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#include <pcicfg.h>
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#include <dhd_pcie.h>
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#include <dhd_linux.h>
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#include <rk_dhd_pcie_linux.h>
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#ifdef OEM_ANDROID
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#ifdef CONFIG_ARCH_MSM
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#if defined(CONFIG_PCI_MSM) || defined(CONFIG_ARCH_MSM8996)
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@@ -617,6 +618,8 @@ dhd_bus_is_rc_ep_l1ss_capable(dhd_bus_t *bus)
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uint32 rc_l1ss_cap;
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uint32 ep_l1ss_cap;
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if (IS_ENABLED(CONFIG_PCIEASPM_ROCKCHIP_WIFI_EXTENSION))
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return rk_dhd_bus_is_rc_ep_l1ss_capable(bus);
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/* RC Extendend Capacility */
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rc_l1ss_cap = dhdpcie_access_cap(bus->rc_dev, PCIE_EXTCAP_ID_L1SS,
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PCIE_EXTCAP_L1SS_CONTROL_OFFSET, TRUE, FALSE, 0);
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@@ -0,0 +1,36 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Rockchip PCIe Apis For WIFI
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*
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* Copyright (c) 2022, Rockchip Electronics Co., Ltd.
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*/
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#ifndef __RK_DHD_PCIE_LINUX_H__
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#define __RK_DHD_PCIE_LINUX_H__
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#include <typedefs.h>
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#include <sbchipc.h>
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#include <pcie_core.h>
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#include <dhd_pcie.h>
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#include <linux/aspm_ext.h>
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static inline void
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rk_dhd_bus_l1ss_enable_rc_ep(dhd_bus_t *bus, bool enable)
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{
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if (!bus->rc_ep_aspm_cap || !bus->rc_ep_l1ss_cap) {
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pr_err("%s: NOT L1SS CAPABLE rc_ep_aspm_cap: %d rc_ep_l1ss_cap: %d\n",
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__func__, bus->rc_ep_aspm_cap, bus->rc_ep_l1ss_cap);
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return;
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}
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/* Disable ASPM of RC and EP */
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pcie_aspm_ext_l1ss_enable(bus->dev, bus->rc_dev, enable);
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}
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static inline bool
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rk_dhd_bus_is_rc_ep_l1ss_capable(dhd_bus_t *bus)
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{
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return pcie_aspm_ext_is_rc_ep_l1ss_capable(bus->dev, bus->rc_dev);
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}
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#endif /* __RK_DHD_PCIE_LINUX_H__ */
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