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clk: rockchip: rk3288: not use usbphy_480m temporarily

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This commit is contained in:
dkl
2014-04-01 09:28:10 +08:00
parent 175e2ce4f5
commit 9e47e4ddf4
1 changed files with 15 additions and 8 deletions
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23
arch/arm/boot/dts/rk3288-clocks.dtsi
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@@ -59,6 +59,13 @@
#clock-cells = <0>;
};
dummy_480m: dummy_480m {
compatible = "rockchip,rk-fixed-clock";
clock-output-names = "dummy_480m";
clock-frequency = <0>;
#clock-cells = <0>;
};
i2s_clkin: i2s_clkin {
compatible = "rockchip,rk-fixed-clock";
clock-output-names = "i2s_clkin";
@@ -839,7 +846,7 @@
clk_uart0_pll: clk_uart0_pll_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <13 2>;
clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>, <&clk_npll>;
clock-output-names = "clk_uart0_pll";
#clock-cells = <0>;
};
@@ -1433,7 +1440,7 @@
aclk_rga: aclk_rga_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>;
clock-output-names = "aclk_rga";
#clock-cells = <0>;
#clock-init-cells = <1>;
@@ -1455,7 +1462,7 @@
clk_rga: clk_rga_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>;
clock-output-names = "clk_rga";
#clock-cells = <0>;
#clock-init-cells = <1>;
@@ -1484,7 +1491,7 @@
aclk_vio0: aclk_vio0_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>;
clock-output-names = "aclk_vio0";
#clock-cells = <0>;
#clock-init-cells = <1>;
@@ -1506,7 +1513,7 @@
aclk_vio1: aclk_vio1_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>;
clock-output-names = "aclk_vio1";
#clock-cells = <0>;
#clock-init-cells = <1>;
@@ -1535,7 +1542,7 @@
clk_vepu: clk_vepu_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>;
clock-output-names = "clk_vepu";
#clock-cells = <0>;
#clock-init-cells = <1>;
@@ -1557,7 +1564,7 @@
clk_vdpu: clk_vdpu_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>;
clock-output-names = "clk_vdpu";
#clock-cells = <0>;
#clock-init-cells = <1>;
@@ -1617,7 +1624,7 @@
clk_gpu: clk_gpu_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>, <&clk_npll>;
clock-output-names = "clk_gpu";
#clock-cells = <0>;
#clock-init-cells = <1>;